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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2018-11-16 21:42:34 +0100
committerKevin Hilman <khilman@baylibre.com>2018-11-29 01:49:03 +0100
commit523b8b31d3e1292b69f233e1a1814151878d6ac8 (patch)
tree0eb5b752f7353fc4687e7ed7ebfd7006959b7019 /.cocciconfig
parentARM: dts: meson: consistently disable pin bias (diff)
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ARM: dts: meson: add the TIMER B/C/D interrupts
The timer on Meson6/Meson8/Meson8b SoCs has four internal timer events. For each of these a separate interrupt exists. Pass these interrupts to allow using the timers other than TIMER A. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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