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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2016-04-04 16:35:09 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-04-30 18:26:55 +0200
commit107e15fc1f8d6ef69eac5f175971252f76e82f0d (patch)
tree7b99ffdc1e6cd95024ceb6de77764b370849424b /.gitignore
parentserial: 8250_pci: report DCD and DSR signals as active for Bay Trail (diff)
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serial: 8250_mid: use proper bar for DNV platform
Unlike Intel Medfield and Tangier platforms DNV uses PCI BAR0 for IO compatible resources and BAR1 for MMIO. We need latter in a way to support DMA. Introduce an additional field in the internal structure and pass PCI BAR based on device ID. Reported-by: "Lai, Poey Seng" <poey.seng.lai@intel.com> Fixes: 6ede6dcd87aa ("serial: 8250_mid: add support for DMA engine handling from UART MMIO") Cc: stable@vger.kernel.org Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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