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| author | Dmitry Osipenko <digetx@gmail.com> | 2018-01-10 14:59:44 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-03-12 13:59:06 +0100 |
| commit | c485ad63abb4b30a3654e80fef9708a181447965 (patch) | |
| tree | 40c3433842269e3bbbd340f75106a339de9bc0e3 /.gitignore | |
| parent | clk: tegra20: Correct PLL_C_OUT1 setup (diff) | |
| download | linux-c485ad63abb4b30a3654e80fef9708a181447965.tar.xz linux-c485ad63abb4b30a3654e80fef9708a181447965.zip | |
clk: tegra: Specify VDE clock rate
Currently VDE clock rate is determined by clock config left from
bootloader, let's not rely on it and explicitly specify the clock
rate in the CCF driver.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to '.gitignore')
0 files changed, 0 insertions, 0 deletions