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authorWill Deacon <will.deacon@arm.com>2018-11-21 16:07:00 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2018-11-23 19:44:16 +0100
commit4f9f49646a5733c0c2bd49940673dde89a9c5add (patch)
tree8b97582d7df983e4a364554868a27b542e6c50d9
parentarm64: sysreg: fix sparse warnings (diff)
downloadlinux-4f9f49646a5733c0c2bd49940673dde89a9c5add.tar.xz
linux-4f9f49646a5733c0c2bd49940673dde89a9c5add.zip
arm64: cpufeature: Fix mismerge of CONFIG_ARM64_SSBD block
When merging support for SSBD and the CRC32 instructions, the conflict resolution for the new capability entries in arm64_features[] inadvertedly predicated the availability of the CRC32 instructions on CONFIG_ARM64_SSBD, despite the functionality being entirely unrelated. Move the #ifdef CONFIG_ARM64_SSBD down so that it only covers the SSBD capability. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to '')
-rw-r--r--arch/arm64/kernel/cpufeature.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index af50064dea51..aec5ecb85737 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1333,7 +1333,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.cpu_enable = cpu_enable_hw_dbm,
},
#endif
-#ifdef CONFIG_ARM64_SSBD
{
.desc = "CRC32 instructions",
.capability = ARM64_HAS_CRC32,
@@ -1343,6 +1342,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64ISAR0_CRC32_SHIFT,
.min_field_value = 1,
},
+#ifdef CONFIG_ARM64_SSBD
{
.desc = "Speculative Store Bypassing Safe (SSBS)",
.capability = ARM64_SSBS,