diff options
| author | Michael Chan <mchan@broadcom.com> | 2014-01-01 08:22:33 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-01-02 04:03:38 +0100 |
| commit | 41033b65b98388cb255c0307ea869856f71ca80d (patch) | |
| tree | 73e011d9b78368cbf402cd7372c3f55788a978e8 | |
| parent | bnx2: Advertise nothing when speed is forced (diff) | |
| download | linux-41033b65b98388cb255c0307ea869856f71ca80d.tar.xz linux-41033b65b98388cb255c0307ea869856f71ca80d.zip | |
bnx2: Enable auto-mdix when autoneg is disabled.
Auto-mdix currently only works if autoneg is enabled. This patch enables
auto-mdix all the time by setting a bit in a PHY register. Define
meaningful constants for this PHY registers.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/ethernet/broadcom/bnx2.c | 12 | ||||
| -rw-r--r-- | drivers/net/ethernet/broadcom/bnx2.h | 6 |
2 files changed, 15 insertions, 3 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2.c b/drivers/net/ethernet/broadcom/bnx2.c index 1ae3348df3ef..b380c69d57a5 100644 --- a/drivers/net/ethernet/broadcom/bnx2.c +++ b/drivers/net/ethernet/broadcom/bnx2.c @@ -2343,9 +2343,15 @@ bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy) } /* ethernet@wirespeed */ - bnx2_write_phy(bp, 0x18, 0x7007); - bnx2_read_phy(bp, 0x18, &val); - bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4)); + bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL); + bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val); + val |= AUX_CTL_MISC_CTL_WR | AUX_CTL_MISC_CTL_WIRESPEED; + + /* auto-mdix */ + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) + val |= AUX_CTL_MISC_CTL_AUTOMDIX; + + bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val); return 0; } diff --git a/drivers/net/ethernet/broadcom/bnx2.h b/drivers/net/ethernet/broadcom/bnx2.h index 18cb2d23e56b..39f40d113254 100644 --- a/drivers/net/ethernet/broadcom/bnx2.h +++ b/drivers/net/ethernet/broadcom/bnx2.h @@ -6471,6 +6471,12 @@ struct l2_fhdr { #define BCM5708S_TX_ACTL3 0x17 +#define MII_BNX2_AUX_CTL 0x18 +#define AUX_CTL_MISC_CTL 0x7007 +#define AUX_CTL_MISC_CTL_WIRESPEED (1 << 4) +#define AUX_CTL_MISC_CTL_AUTOMDIX (1 << 9) +#define AUX_CTL_MISC_CTL_WR (1 << 15) + #define MII_BNX2_DSP_RW_PORT 0x15 #define MII_BNX2_DSP_ADDRESS 0x17 #define MII_BNX2_DSP_EXPAND_REG 0x0f00 |