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authorChanwoo Choi <cw00.choi@samsung.com>2014-10-27 02:11:58 +0100
committerSylwester Nawrocki <s.nawrocki@samsung.com>2014-10-30 19:53:03 +0100
commit6233fe38048a80a9fa111ddb166ce9e8e0f5f1b3 (patch)
tree4cbf0c085326945e0b794411d0c51a16329fc643
parentLinux 3.18-rc1 (diff)
downloadlinux-6233fe38048a80a9fa111ddb166ce9e8e0f5f1b3.tar.xz
linux-6233fe38048a80a9fa111ddb166ce9e8e0f5f1b3.zip
clk: samsung: Document binding for Exynos4415 clock controller
This patch adds DT binding documentation for Exynos4415 SoC system clock controllers. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-rw-r--r--Documentation/devicetree/bindings/clock/exynos4415-clock.txt38
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diff --git a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
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+* Samsung Exynos4415 Clock Controller
+
+The Exynos4415 clock controller generates and supplies clock to various
+consumer devices within the Exynos4415 SoC.
+
+Required properties:
+
+- compatible: should be one of the following:
+ - "samsung,exynos4415-cmu" - for the main system clocks controller
+ (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
+ - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
+ Controller (DMC) domain clock controller.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos4415.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+ cmu: clock-controller@10030000 {
+ compatible = "samsung,exynos4415-cmu";
+ reg = <0x10030000 0x18000>;
+ #clock-cells = <1>;
+ };
+
+ cmu-dmc: clock-controller@105C0000 {
+ compatible = "samsung,exynos4415-cmu-dmc";
+ reg = <0x105C0000 0x3000>;
+ #clock-cells = <1>;
+ };