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| author | Tero Kristo <t-kristo@ti.com> | 2014-02-27 16:21:33 +0100 |
|---|---|---|
| committer | Tero Kristo <t-kristo@ti.com> | 2014-05-28 11:30:07 +0200 |
| commit | 9fa160cb9f2f51ef8274df7b4f390edf6ae491c3 (patch) | |
| tree | 29cf62eb167e51f1a4b2b9d7c882cddffea1ad36 | |
| parent | CLK: TI: APLL: add support for omap2 aplls (diff) | |
| download | linux-9fa160cb9f2f51ef8274df7b4f390edf6ae491c3.tar.xz linux-9fa160cb9f2f51ef8274df7b4f390edf6ae491c3.zip | |
CLK: TI: gate: fixed DT binding documentation bugs
ti,composite-gate-clock documentation was missing, also the register
offset examples were wrong.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
| -rw-r--r-- | Documentation/devicetree/bindings/clock/ti/gate.txt | 29 |
1 files changed, 25 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt index 125281aaa4ca..03f8fdee62a7 100644 --- a/Documentation/devicetree/bindings/clock/ti/gate.txt +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt @@ -25,6 +25,11 @@ Required properties: to map clockdomains properly "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling, required for a hardware errata + "ti,composite-gate-clock" - composite gate clock, to be part of composite + clock + "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait + for clock to be active before returning + from clk_enable() - #clock-cells : from common clock binding; shall be set to 0 - clocks : link to phandle of parent clock - reg : offset for register controlling adjustable gate, not needed for @@ -41,7 +46,7 @@ Examples: #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&core_96m_fck>; - reg = <0x48004a00 0x4>; + reg = <0x0a00>; ti,bit-shift = <25>; }; @@ -57,7 +62,7 @@ Examples: #clock-cells = <0>; compatible = "ti,dss-gate-clock"; clocks = <&dpll4_m4x2_ck>; - reg = <0x48004e00 0x4>; + reg = <0x0e00>; ti,bit-shift = <0>; }; @@ -65,7 +70,7 @@ Examples: #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&ipss_ick>; - reg = <0x4800259c 0x4>; + reg = <0x059c>; ti,bit-shift = <1>; }; @@ -80,6 +85,22 @@ Examples: compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m2x2_mul_ck>; ti,bit-shift = <0x1b>; - reg = <0x48004d00 0x4>; + reg = <0x0d00>; ti,set-bit-to-disable; }; + + vlynq_gate_fck: vlynq_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <3>; + reg = <0x0200>; + }; + + sys_clkout2_src_gate: sys_clkout2_src_gate { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <15>; + reg = <0x0070>; + }; |