diff options
author | Viresh Kumar <viresh.kumar@st.com> | 2012-02-01 11:42:28 +0100 |
---|---|---|
committer | Vinod Koul <vinod.koul@linux.intel.com> | 2012-02-22 13:45:39 +0100 |
commit | a1c46016794fdd83b7993303915ec7f4a06682b7 (patch) | |
tree | 92b11c6c5e156025eacdc11110e4d8f15f3c8b13 | |
parent | dmaengine/dw_dmac: Fix dw_dmac user drivers to adapt to slave_config changes (diff) | |
download | linux-a1c46016794fdd83b7993303915ec7f4a06682b7.tar.xz linux-a1c46016794fdd83b7993303915ec7f4a06682b7.zip |
dmaengine/dw_dmac: Remove unused fields in struct dw_dma_slave
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
-rw-r--r-- | drivers/dma/dw_dmac_regs.h | 12 | ||||
-rw-r--r-- | include/linux/dw_dmac.h | 38 |
2 files changed, 12 insertions, 38 deletions
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h index 2005d301803d..eec0481a12f7 100644 --- a/drivers/dma/dw_dmac_regs.h +++ b/drivers/dma/dw_dmac_regs.h @@ -13,6 +13,18 @@ #define DW_DMA_MAX_NR_CHANNELS 8 +/* flow controller */ +enum dw_dma_fc { + DW_DMA_FC_D_M2M, + DW_DMA_FC_D_M2P, + DW_DMA_FC_D_P2M, + DW_DMA_FC_D_P2P, + DW_DMA_FC_P_P2M, + DW_DMA_FC_SP_P2P, + DW_DMA_FC_P_M2P, + DW_DMA_FC_DP_P2P, +}; + /* * Redefine this macro to handle differences between 32- and 64-bit * addressing, big vs. little endian, etc. diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h index f2c64f92c4a0..2412e02d7c0f 100644 --- a/include/linux/dw_dmac.h +++ b/include/linux/dw_dmac.h @@ -31,18 +31,6 @@ struct dw_dma_platform_data { unsigned char chan_priority; }; -/** - * enum dw_dma_slave_width - DMA slave register access width. - * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses - * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses - * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses - */ -enum dw_dma_slave_width { - DW_DMA_SLAVE_WIDTH_8BIT, - DW_DMA_SLAVE_WIDTH_16BIT, - DW_DMA_SLAVE_WIDTH_32BIT, -}; - /* bursts size */ enum dw_dma_msize { DW_DMA_MSIZE_1, @@ -55,47 +43,21 @@ enum dw_dma_msize { DW_DMA_MSIZE_256, }; -/* flow controller */ -enum dw_dma_fc { - DW_DMA_FC_D_M2M, - DW_DMA_FC_D_M2P, - DW_DMA_FC_D_P2M, - DW_DMA_FC_D_P2P, - DW_DMA_FC_P_P2M, - DW_DMA_FC_SP_P2P, - DW_DMA_FC_P_M2P, - DW_DMA_FC_DP_P2P, -}; - /** * struct dw_dma_slave - Controller-specific information about a slave * * @dma_dev: required DMA master device - * @tx_reg: physical address of data register used for - * memory-to-peripheral transfers - * @rx_reg: physical address of data register used for - * peripheral-to-memory transfers - * @reg_width: peripheral register width * @cfg_hi: Platform-specific initializer for the CFG_HI register * @cfg_lo: Platform-specific initializer for the CFG_LO register * @src_master: src master for transfers on allocated channel. * @dst_master: dest master for transfers on allocated channel. - * @src_msize: src burst size. - * @dst_msize: dest burst size. - * @fc: flow controller for DMA transfer */ struct dw_dma_slave { struct device *dma_dev; - dma_addr_t tx_reg; - dma_addr_t rx_reg; - enum dw_dma_slave_width reg_width; u32 cfg_hi; u32 cfg_lo; u8 src_master; u8 dst_master; - u8 src_msize; - u8 dst_msize; - u8 fc; }; /* Platform-configurable bits in CFG_HI */ |