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| author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2006-02-15 10:25:48 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-03-21 14:27:45 +0100 |
| commit | 37caa934af02bc01d0e1366a49e1c89360fa0f29 (patch) | |
| tree | 96f0a41a3edbd0404358a92e5af5c1739ce311ac | |
| parent | [MIPS] MIPS64 R2 optimizations for 64-bit endianess swapping. (diff) | |
| download | linux-37caa934af02bc01d0e1366a49e1c89360fa0f29.tar.xz linux-37caa934af02bc01d0e1366a49e1c89360fa0f29.zip | |
[MIPS] sc-rm7k.c cleanup
Use blast_scache_range, blast_inv_scache_range for rm7k scache routine.
Output code should be logically same.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/mm/sc-rm7k.c | 25 | ||||
| -rw-r--r-- | include/asm-mips/r4kcache.h | 1 |
2 files changed, 10 insertions, 16 deletions
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c index 9e8ff8badb19..3b6cc9ba1b05 100644 --- a/arch/mips/mm/sc-rm7k.c +++ b/arch/mips/mm/sc-rm7k.c @@ -9,6 +9,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/mm.h> +#include <linux/bitops.h> #include <asm/addrspace.h> #include <asm/bcache.h> @@ -43,14 +44,7 @@ static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size) /* Catch bad driver code */ BUG_ON(size == 0); - a = addr & ~(sc_lsize - 1); - end = (addr + size - 1) & ~(sc_lsize - 1); - while (1) { - flush_scache_line(a); /* Hit_Writeback_Inv_SD */ - if (a == end) - break; - a += sc_lsize; - } + blast_scache_range(addr, addr + size); if (!rm7k_tcache_enabled) return; @@ -74,14 +68,7 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size) /* Catch bad driver code */ BUG_ON(size == 0); - a = addr & ~(sc_lsize - 1); - end = (addr + size - 1) & ~(sc_lsize - 1); - while (1) { - invalidate_scache_line(a); /* Hit_Invalidate_SD */ - if (a == end) - break; - a += sc_lsize; - } + blast_inv_scache_range(addr, addr + size); if (!rm7k_tcache_enabled) return; @@ -143,11 +130,17 @@ struct bcache_ops rm7k_sc_ops = { void __init rm7k_sc_init(void) { + struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config = read_c0_config(); if ((config & RM7K_CONF_SC)) return; + c->scache.linesz = sc_lsize; + c->scache.ways = 4; + c->scache.waybit= ffs(scache_size / c->scache.ways) - 1; + c->scache.waysize = scache_size / c->scache.ways; + c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n", (scache_size >> 10), sc_lsize); diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index 0bcb79a58ee9..90c374700977 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -303,5 +303,6 @@ __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) /* blast_inv_dcache_range */ __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) #endif /* _ASM_R4KCACHE_H */ |