diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2005-07-03 18:53:25 +0200 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2005-07-03 18:53:25 +0200 |
| commit | 0d670b413f042eccdffc45bafb9840244752707f (patch) | |
| tree | 5658514d70f4a62ae2268f1837a3d05e3b87bfba | |
| parent | [PATCH] ARM: 2785/1: S3C24XX - serial calls request_irq() with IRQs disabled (diff) | |
| download | linux-0d670b413f042eccdffc45bafb9840244752707f.tar.xz linux-0d670b413f042eccdffc45bafb9840244752707f.zip | |
[PATCH] ARM: 2784/1: Fix the block cache flush operation range
Patch from Catalin Marinas
The range for the ARMv6 block cache operations is inclusive but the
kernel doesn't re-calculate the end address, causing a page fault when
used (this only happens with support for cache aliasing, otherwise the
blk_flush_kern_dcache_page() is not called). This patch subtracts
L1_CACHE_BYTES from the end address.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| -rw-r--r-- | arch/arm/mm/blockops.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mm/blockops.c b/arch/arm/mm/blockops.c index 806c6eeb1b0c..4f5ee2d08996 100644 --- a/arch/arm/mm/blockops.c +++ b/arch/arm/mm/blockops.c @@ -25,13 +25,14 @@ blk_flush_kern_dcache_page(void *kaddr) { asm( "add r1, r0, %0 \n\ + sub r1, r1, %1 \n\ 1: .word 0xec401f0e @ mcrr p15, 0, r0, r1, c14, 0 @ blocking \n\ mov r0, #0 \n\ mcr p15, 0, r0, c7, c5, 0 \n\ mcr p15, 0, r0, c7, c10, 4 \n\ mov pc, lr" : - : "I" (PAGE_SIZE)); + : "I" (PAGE_SIZE), "I" (L1_CACHE_BYTES)); } /* |