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author | Elaine Zhang <zhangqing@rock-chips.com> | 2017-09-01 04:01:46 +0200 |
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committer | Heiko Stuebner <heiko@sntech.de> | 2017-09-17 01:55:36 +0200 |
commit | 00e6751ffc9e6e0651e514961316fd15f0409683 (patch) | |
tree | c1caf461f8ea280c672a8044db79c37c604cd535 | |
parent | clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs error (diff) | |
download | linux-00e6751ffc9e6e0651e514961316fd15f0409683.tar.xz linux-00e6751ffc9e6e0651e514961316fd15f0409683.zip |
clk: rockchip: add sclk_timer5 as critical clock on rk3128
sclk_timer5 is for arm arch counter, so need always on.
but no dts node to handle this clk, so make it as critical clock
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r-- | drivers/clk/rockchip/clk-rk3128.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c index ce02d2cff608..5970a50671b9 100644 --- a/drivers/clk/rockchip/clk-rk3128.c +++ b/drivers/clk/rockchip/clk-rk3128.c @@ -578,6 +578,7 @@ static const char *const rk3128_critical_clocks[] __initconst = { "hclk_peri", "pclk_peri", "pclk_pmu", + "sclk_timer5", }; static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np) |