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| author | Jassi Brar <jassi.brar@samsung.com> | 2010-01-18 08:15:08 +0100 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2010-01-18 09:26:58 +0100 |
| commit | 87315a802a8aab9d986858fcf2230726c1b5c598 (patch) | |
| tree | 0114717eae50811d33b7cf3e7286a2e67fea3960 | |
| parent | ARM: S3C64XX: SPI: Add SPI controller register base (diff) | |
| download | linux-87315a802a8aab9d986858fcf2230726c1b5c598.tar.xz linux-87315a802a8aab9d986858fcf2230726c1b5c598.zip | |
ARM: S3C64XX: SPI: Define SPI-48M clock sources
Defined special 48MHz clock sources for SPI-0,1.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| -rw-r--r-- | arch/arm/plat-s3c64xx/clock.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c index ae5883c00e7a..2989c3a2e94d 100644 --- a/arch/arm/plat-s3c64xx/clock.c +++ b/arch/arm/plat-s3c64xx/clock.c @@ -141,6 +141,18 @@ static struct clk init_clocks_disable[] = { .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_SPI1, }, { + .name = "spi_48m", + .id = 0, + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, + }, { + .name = "spi_48m", + .id = 1, + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, + }, { .name = "48m", .id = 0, .parent = &clk_48m, |