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| author | Lennert Buytenhek <buytenh@wantstofly.org> | 2008-06-22 22:45:09 +0200 |
|---|---|---|
| committer | Lennert Buytenhek <buytenh@marvell.com> | 2008-06-22 22:45:09 +0200 |
| commit | a9311cfed241ebcd6b5f9be5c8c6d519bf22f9e7 (patch) | |
| tree | e8d8fdf57be1e05dfb78005e71e4f62a109633c5 | |
| parent | [ARM] Feroceon: 88fr571-vd support (diff) | |
| download | linux-a9311cfed241ebcd6b5f9be5c8c6d519bf22f9e7.tar.xz linux-a9311cfed241ebcd6b5f9be5c8c6d519bf22f9e7.zip | |
[ARM] Orion: PCIe x4/x1 detection support
The Discovery Duo (MV78xx0) has two x4 PCIe ports which can either
be used in x4 mode or in quad x1 mode. This patch adds an accessor
function to the generic plat-orion PCIe handling code to detect in
which of the two modes we're running (which is determined by strap
pins and/or configured by the bootloader).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
| -rw-r--r-- | arch/arm/plat-orion/pcie.c | 6 | ||||
| -rw-r--r-- | include/asm-arm/plat-orion/pcie.h | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index abfda53f1800..ca32c60e14d7 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c @@ -39,6 +39,7 @@ #define PCIE_CONF_DATA_OFF 0x18fc #define PCIE_MASK_OFF 0x1910 #define PCIE_CTRL_OFF 0x1a00 +#define PCIE_CTRL_X1_MODE 0x0001 #define PCIE_STAT_OFF 0x1a04 #define PCIE_STAT_DEV_OFFS 20 #define PCIE_STAT_DEV_MASK 0x1f @@ -62,6 +63,11 @@ int orion_pcie_link_up(void __iomem *base) return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); } +int __init orion_pcie_x4_mode(void __iomem *base) +{ + return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE); +} + int orion_pcie_get_local_bus_nr(void __iomem *base) { u32 stat = readl(base + PCIE_STAT_OFF); diff --git a/include/asm-arm/plat-orion/pcie.h b/include/asm-arm/plat-orion/pcie.h index 6434ac685d21..e61b7bd97af5 100644 --- a/include/asm-arm/plat-orion/pcie.h +++ b/include/asm-arm/plat-orion/pcie.h @@ -14,6 +14,7 @@ u32 orion_pcie_dev_id(void __iomem *base); u32 orion_pcie_rev(void __iomem *base); int orion_pcie_link_up(void __iomem *base); +int orion_pcie_x4_mode(void __iomem *base); int orion_pcie_get_local_bus_nr(void __iomem *base); void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); void orion_pcie_setup(void __iomem *base, |