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author | Heiko Stuebner <heiko@sntech.de> | 2018-01-27 23:21:12 +0100 |
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committer | Heiko Stuebner <heiko@sntech.de> | 2018-10-11 14:57:25 +0200 |
commit | 5f697a0e311c1e8e3cf56edaf1b757027f5275b0 (patch) | |
tree | 92608b7d5be4ef8ca5ee1fe3b628ab090c4b501f | |
parent | clk: rockchip: fix wrong mmc sample phase shift for rk3328 (diff) | |
download | linux-5f697a0e311c1e8e3cf56edaf1b757027f5275b0.tar.xz linux-5f697a0e311c1e8e3cf56edaf1b757027f5275b0.zip |
clk: rockchip: add clock-id for HCLK_HDMI on rk3066
RK3066 and RK3188 share most of the clock controller but the rk3066 does
have an internal hdmi encoder and associated clock. Therefore add a
clock-id so that this clock can be used.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r-- | include/dt-bindings/clock/rk3188-cru-common.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index b9462b7d3dfe..dc2101a634be 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -139,8 +139,9 @@ #define HCLK_CIF1 470 #define HCLK_VEPU 471 #define HCLK_VDPU 472 +#define HCLK_HDMI 473 -#define CLK_NR_CLKS (HCLK_VDPU + 1) +#define CLK_NR_CLKS (HCLK_HDMI + 1) /* soft-reset indices */ #define SRST_MCORE 2 |