diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2011-07-12 03:02:04 +0200 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2011-07-13 20:49:40 +0200 |
| commit | 6340211c5f4775a52c98052fb5661565f79249fd (patch) | |
| tree | 200d247fd75a5212330cf46785ca8a1678577563 | |
| parent | ath5k: fix reference clock usec duration setting restore (diff) | |
| download | linux-6340211c5f4775a52c98052fb5661565f79249fd.tar.xz linux-6340211c5f4775a52c98052fb5661565f79249fd.zip | |
ath5k: disable 32KHz sleep clock operation by default
While 32 KHz sleep clock might provide some power saving benefits,
it is also a major source of stability issues, on OpenWrt it produced
some reproducible data bus errors on register accesses on several
different MIPS platforms.
All the Atheros drivers that I can find do not enable this feature,
so it makes sense to leave it disabled in ath5k as well.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Acked-by: Nick Kossifidis <mickflemm@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
| -rw-r--r-- | drivers/net/wireless/ath/ath5k/ath5k.h | 2 | ||||
| -rw-r--r-- | drivers/net/wireless/ath/ath5k/debug.c | 3 | ||||
| -rw-r--r-- | drivers/net/wireless/ath/ath5k/reset.c | 11 |
3 files changed, 13 insertions, 3 deletions
diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h index 50d758036126..8ff17941bb28 100644 --- a/drivers/net/wireless/ath/ath5k/ath5k.h +++ b/drivers/net/wireless/ath/ath5k/ath5k.h @@ -1067,6 +1067,8 @@ struct ath5k_hw { u8 ah_retry_long; u8 ah_retry_short; + u32 ah_use_32khz_clock; + u8 ah_coverage_class; bool ah_ack_bitrate_high; u8 ah_bwmode; diff --git a/drivers/net/wireless/ath/ath5k/debug.c b/drivers/net/wireless/ath/ath5k/debug.c index ae1112bfa1c1..4edca7072d53 100644 --- a/drivers/net/wireless/ath/ath5k/debug.c +++ b/drivers/net/wireless/ath/ath5k/debug.c @@ -922,6 +922,9 @@ ath5k_debug_init_device(struct ath5k_softc *sc) debugfs_create_file("queue", S_IWUSR | S_IRUSR, phydir, sc, &fops_queue); + + debugfs_create_bool("32khz_clock", S_IWUSR | S_IRUSR, phydir, + &sc->ah->ah_use_32khz_clock); } /* functions used in other places */ diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c index 0e89fc9a75a7..9f9c2ad3ca66 100644 --- a/drivers/net/wireless/ath/ath5k/reset.c +++ b/drivers/net/wireless/ath/ath5k/reset.c @@ -1287,11 +1287,16 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, ath5k_hw_dma_init(ah); - /* Enable 32KHz clock function for AR5212+ chips + /* + * Enable 32KHz clock function for AR5212+ chips * Set clocks to 32KHz operation and use an * external 32KHz crystal when sleeping if one - * exists */ - if (ah->ah_version == AR5K_AR5212 && + * exists. + * Disabled by default because it is also disabled in + * other drivers and it is known to cause stability + * issues on some devices + */ + if (ah->ah_use_32khz_clock && ah->ah_version == AR5K_AR5212 && op_mode != NL80211_IFTYPE_AP) ath5k_hw_set_sleep_clock(ah, true); |