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authorHeiner Kallweit <hkallweit1@gmail.com>2017-02-07 22:35:59 +0100
committerUlf Hansson <ulf.hansson@linaro.org>2017-02-14 09:10:58 +0100
commite21e6fdd2935e147f845de7ddf39d6204a075a46 (patch)
tree7e74a7f27b648d722021740e44ccc0b82abc8cd6
parentmmc: meson-gx: remove unneeded checks in remove (diff)
downloadlinux-e21e6fdd2935e147f845de7ddf39d6204a075a46.tar.xz
linux-e21e6fdd2935e147f845de7ddf39d6204a075a46.zip
mmc: meson-gx: add support for HS400 mode
Add support for HS400 mode. The driver still misses support for tuning, therefore highspeed modes like HS400 might not work under all circumstances yet. Successfully tested on a Odroid C2 (S905 GXBB). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-rw-r--r--drivers/mmc/host/meson-gx-mmc.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 3cc6334acdb1..5a959783304b 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -83,6 +83,7 @@
#define CFG_RC_CC_MASK 0xf
#define CFG_STOP_CLOCK BIT(22)
#define CFG_CLK_ALWAYS_ON BIT(18)
+#define CFG_CHK_DS BIT(20)
#define CFG_AUTO_CLK BIT(23)
#define SD_EMMC_STATUS 0x48
@@ -408,6 +409,16 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
val &= ~(CFG_RC_CC_MASK << CFG_RC_CC_SHIFT);
val |= ilog2(SD_EMMC_CFG_CMD_GAP) << CFG_RC_CC_SHIFT;
+ val &= ~CFG_DDR;
+ if (ios->timing == MMC_TIMING_UHS_DDR50 ||
+ ios->timing == MMC_TIMING_MMC_DDR52 ||
+ ios->timing == MMC_TIMING_MMC_HS400)
+ val |= CFG_DDR;
+
+ val &= ~CFG_CHK_DS;
+ if (ios->timing == MMC_TIMING_MMC_HS400)
+ val |= CFG_CHK_DS;
+
writel(val, host->regs + SD_EMMC_CFG);
if (val != orig)