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authorAndrew Isaacson <adi@broadcom.com>2005-10-20 08:56:20 +0200
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 20:32:46 +0200
commit93ce2f524e96571711029884e6340c790a029b94 (patch)
tree1cb69ac513d01b25a2c300c90a2f11c69c0290e9
parentSibyte header cleanup (diff)
downloadlinux-93ce2f524e96571711029884e6340c790a029b94.tar.xz
linux-93ce2f524e96571711029884e6340c790a029b94.zip
Add support for SB1A CPU.
Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/kernel/cpu-probe.c3
-rw-r--r--arch/mips/kernel/proc.c1
-rw-r--r--arch/mips/mm/tlbex.c1
-rw-r--r--include/asm-mips/addrspace.h2
-rw-r--r--include/asm-mips/cpu.h4
5 files changed, 9 insertions, 2 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f7a841573b84..a263fb7a3971 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -623,6 +623,9 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
#endif
break;
+ case PRID_IMP_SB1A:
+ c->cputype = CPU_SB1A;
+ break;
}
}
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index f2b0446e44bc..86fe15b273cd 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -56,6 +56,7 @@ static const char *cpu_name[] = {
[CPU_5KC] = "MIPS 5Kc",
[CPU_R4310] = "R4310",
[CPU_SB1] = "SiByte SB1",
+ [CPU_SB1A] = "SiByte SB1A",
[CPU_TX3912] = "TX3912",
[CPU_TX3922] = "TX3922",
[CPU_TX3927] = "TX3927",
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 240537d263ff..0f9485806bac 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -854,6 +854,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
case CPU_R12000:
case CPU_4KC:
case CPU_SB1:
+ case CPU_SB1A:
case CPU_4KSC:
case CPU_20KC:
case CPU_25KF:
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 16c1c08d0a03..42520cc84b0f 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -162,7 +162,7 @@
#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */
#endif
-#if defined(CONFIG_CPU_SB1)
+#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
#define KUSIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
#define KUSIZE_64 _LLCONST_(0x0000100000000000) /* 2^^44 */
#define K0SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 46b2a8dc2ee0..48eac296060f 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -93,6 +93,7 @@
*/
#define PRID_IMP_SB1 0x0100
+#define PRID_IMP_SB1A 0x1100
/*
* These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
@@ -194,7 +195,8 @@
#define CPU_AU1200 59
#define CPU_34K 60
#define CPU_PR4450 61
-#define CPU_LAST 61
+#define CPU_SB1A 62
+#define CPU_LAST 62
/*
* ISA Level encodings