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| author | Len Brown <len.brown@intel.com> | 2015-12-03 07:35:36 +0100 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2016-02-17 07:43:05 +0100 |
| commit | f0057310b40efe9f797ff337e9464e6a6fb9d782 (patch) | |
| tree | d6a8ee3ea486f39745f2f8f38acc3c40d03b670b | |
| parent | tools/power turbostat: decode HWP registers (diff) | |
| download | linux-f0057310b40efe9f797ff337e9464e6a6fb9d782.tar.xz linux-f0057310b40efe9f797ff337e9464e6a6fb9d782.zip | |
tools/power turbostat: Decode MSR_MISC_PWR_MGMT
This MSR is helpful to show if P-state HW coordination
is enabled or disabled.
Signed-off-by: Len Brown <len.brown@intel.com>
| -rw-r--r-- | tools/power/x86/turbostat/turbostat.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index af3b955aad1d..c600340dfc4e 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -2783,6 +2783,26 @@ void decode_misc_enable_msr(void) msr & (1 << 18) ? "MONITOR" : ""); } +/* + * Decode MSR_MISC_PWR_MGMT + * + * Decode the bits according to the Nehalem documentation + * bit[0] seems to continue to have same meaning going forward + * bit[1] less so... + */ +void decode_misc_pwr_mgmt_msr(void) +{ + unsigned long long msr; + + if (!do_nhm_platform_info) + return; + + if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) + fprintf(stderr, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB)\n", + base_cpu, msr, + msr & (1 << 0) ? "DIS" : "EN", + msr & (1 << 1) ? "EN" : "DIS"); +} void process_cpuid() { @@ -2936,6 +2956,9 @@ void process_cpuid() do_slm_cstates = is_slm(family, model); do_knl_cstates = is_knl(family, model); + if (debug) + decode_misc_pwr_mgmt_msr(); + rapl_probe(family, model); perf_limit_reasons_probe(family, model); |