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authorJoe Perches <joe@perches.com>2007-12-19 02:02:21 +0100
committerTony Luck <tony.luck@intel.com>2007-12-19 02:02:21 +0100
commit313d8e57b074d5f03dfed2755f21ae41a6f0fd5a (patch)
treed2eac737118e16b8bb05f18ca3f5a79856188906
parent[IA64] Avoid unnecessary TLB flushes when allocating memory (diff)
downloadlinux-313d8e57b074d5f03dfed2755f21ae41a6f0fd5a.tar.xz
linux-313d8e57b074d5f03dfed2755f21ae41a6f0fd5a.zip
[IA64] Two trivial spelling fixes
s/addres/address/ s/performanc/performance/ Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
-rw-r--r--arch/ia64/sn/pci/tioce_provider.c2
-rw-r--r--include/asm-ia64/hw_irq.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/ia64/sn/pci/tioce_provider.c b/arch/ia64/sn/pci/tioce_provider.c
index cee9379d44e0..e1a3e19d3d9c 100644
--- a/arch/ia64/sn/pci/tioce_provider.c
+++ b/arch/ia64/sn/pci/tioce_provider.c
@@ -41,7 +41,7 @@
* } else
* do desired mmr access
*
- * According to hw, we can use reads instead of writes to the above addres
+ * According to hw, we can use reads instead of writes to the above address
*
* Note this WAR can only to be used for accessing internal MMR's in the
* TIOCE Coretalk Address Range 0x0 - 0x07ff_ffff. This includes the
diff --git a/include/asm-ia64/hw_irq.h b/include/asm-ia64/hw_irq.h
index bba5baa3c7fc..7e6e3779670a 100644
--- a/include/asm-ia64/hw_irq.h
+++ b/include/asm-ia64/hw_irq.h
@@ -63,7 +63,7 @@ extern int ia64_last_device_vector;
#define IA64_NUM_DEVICE_VECTORS (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1)
#define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */
-#define IA64_PERFMON_VECTOR 0xee /* performanc monitor interrupt vector */
+#define IA64_PERFMON_VECTOR 0xee /* performance monitor interrupt vector */
#define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */
#define IA64_MCA_WAKEUP_VECTOR 0xf0 /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */
#define IA64_IPI_LOCAL_TLB_FLUSH 0xfc /* SMP flush local TLB */