diff options
| author | Peter Griffin <peter.griffin@linaro.org> | 2015-06-10 16:04:00 +0200 |
|---|---|---|
| committer | Maxime Coquelin <maxime.coquelin@st.com> | 2015-07-22 11:03:10 +0200 |
| commit | af4d191e44c9b0ad40b248902881710b117844fb (patch) | |
| tree | d85e962121cc5b0622da54f5f20092d50dc8715c | |
| parent | ARM: STi: DT: Add STiH407 family tsin3 pinctrl configuration (diff) | |
| download | linux-af4d191e44c9b0ad40b248902881710b117844fb.tar.xz linux-af4d191e44c9b0ad40b248902881710b117844fb.zip | |
ARM: STi: DT: Add STiH407 family tsin4 pinctrl configuration
tsin4 can only be configured for serial data transfer. However
depending on board design, two alternate pin configurations
are available. One in pin-controller-front0 and the other in
pin-controller-front1.
pinctrl_tsin4_serial_alt3 is brought out on B2120 reference
design as TSC on NIMA slot of the B2004A daughter board.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
| -rw-r--r-- | arch/arm/boot/dts/stih407-pinctrl.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 760f925e1dcc..50b5bed50d21 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -535,6 +535,18 @@ }; }; }; + + tsin4 { + pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 { + st,pins { + DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>; + ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>; + PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; }; pin-controller-front1 { @@ -548,6 +560,18 @@ interrupts-names = "irqmux"; ranges = <0 0x09210000 0x10000>; + tsin4 { + pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 { + st,pins { + DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; + pio20: pio@09210000 { gpio-controller; #gpio-cells = <1>; |