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| author | Peter Griffin <peter.griffin@linaro.org> | 2015-06-10 16:04:00 +0200 |
|---|---|---|
| committer | Maxime Coquelin <maxime.coquelin@st.com> | 2015-07-22 11:03:10 +0200 |
| commit | dd72896f0d7cbbda0b404ed4b8ad46b56f363fc4 (patch) | |
| tree | b3e5bab14250a4a002c21f492af21d0405c2898c | |
| parent | ARM: STi: DT: Add STiH407 family tsin4 pinctrl configuration (diff) | |
| download | linux-dd72896f0d7cbbda0b404ed4b8ad46b56f363fc4.tar.xz linux-dd72896f0d7cbbda0b404ed4b8ad46b56f363fc4.zip | |
ARM: STi: DT: Add STiH407 family tsin5 pinctrl configuration
tsin5 can only be configured for serial data transfer. However
depending on board design, two alternate tsin5 pin configurations
are available, both in pin-controller-front0.
pinctrl_tsin5_serial_alt1 is brought out on B2120 reference
design as TSD on NIMB slot of the B2004A daughter board.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
| -rw-r--r-- | arch/arm/boot/dts/stih407-pinctrl.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 50b5bed50d21..f513a29fbf33 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -547,6 +547,27 @@ }; }; }; + + tsin5 { + pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 { + st,pins { + DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 { + st,pins { + DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; }; pin-controller-front1 { |