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| author | Dave Airlie <airlied@redhat.com> | 2010-03-31 05:41:35 +0200 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-04-01 04:50:46 +0200 |
| commit | d668046c13024d74af7d04a124ba55f406380fe7 (patch) | |
| tree | 41ef48d72324f88211e279a56bd7f43563a3e366 | |
| parent | drm/radeon/kms: rs400/480 should set common registers. (diff) | |
| download | linux-d668046c13024d74af7d04a124ba55f406380fe7.tar.xz linux-d668046c13024d74af7d04a124ba55f406380fe7.zip | |
drm/radeon/kms: enable ACPI powermanagement mode on radeon gpus.
Some GPUs have an APM/ACPI PM mode selection switch and some BIOSes
set this to APM. We really want this in ACPI mode for Linux.
Signed-off-by: Dave Airlie <airlied@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_reg.h | 1 |
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index c8f4b0300b70..3ae51ada1abf 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -1809,6 +1809,7 @@ void r100_set_common_regs(struct radeon_device *rdev) { struct drm_device *dev = rdev->ddev; bool force_dac2 = false; + u32 tmp; /* set these so they don't interfere with anything */ WREG32(RADEON_OV0_SCALE_CNTL, 0); @@ -1880,6 +1881,12 @@ void r100_set_common_regs(struct radeon_device *rdev) WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); WREG32(RADEON_DAC_CNTL2, dac2_cntl); } + + /* switch PM block to ACPI mode */ + tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); + tmp &= ~RADEON_PM_MODE_SEL; + WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); + } /* diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index 5c0dc082d330..eabbc9cf30a7 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h @@ -346,6 +346,7 @@ # define RADEON_TVPLL_PWRMGT_OFF (1 << 30) # define RADEON_TVCLK_TURNOFF (1 << 31) #define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */ +# define RADEON_PM_MODE_SEL (1 << 13) # define RADEON_TCL_BYPASS_DISABLE (1 << 20) #define RADEON_CLR_CMP_CLR_3D 0x1a24 #define RADEON_CLR_CMP_CLR_DST 0x15c8 |