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| author | Helmut Klein <hgkr.klein@gmail.com> | 2017-03-31 18:54:34 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2017-05-29 14:33:08 +0200 |
| commit | 9dc6bd7678f6ee518c92808886ee087e31f749cf (patch) | |
| tree | 0b9f793c1a92966a48183f3a85f18fc85d36d203 | |
| parent | clk: meson-gxbb: expose SPICC gate (diff) | |
| download | linux-9dc6bd7678f6ee518c92808886ee087e31f749cf.tar.xz linux-9dc6bd7678f6ee518c92808886ee087e31f749cf.zip | |
clk: meson-gxbb: expose UART clocks
Expose the clock ids of the three none AO uarts to the dt-bindings
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Helmut Klein <hgkr.klein@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[tidy the commit message to match similar change]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| -rw-r--r-- | drivers/clk/meson/gxbb.h | 6 | ||||
| -rw-r--r-- | include/dt-bindings/clock/gxbb-clkc.h | 3 |
2 files changed, 6 insertions, 3 deletions
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index e447f02fcd16..16ab5b2707c1 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -196,7 +196,7 @@ /* #define CLKID_SAR_ADC */ #define CLKID_SMART_CARD 24 /* CLKID_RNG0 */ -#define CLKID_UART0 26 +/* CLKID_UART0 */ #define CLKID_SDHC 27 #define CLKID_STREAM 28 #define CLKID_ASYNC_FIFO 29 @@ -218,7 +218,7 @@ #define CLKID_ADC 45 #define CLKID_BLKMV 46 /* CLKID_AIU */ -#define CLKID_UART1 48 +/* CLKID_UART1 */ #define CLKID_G2D 49 /* CLKID_USB0 */ /* CLKID_USB1 */ @@ -238,7 +238,7 @@ /* CLKID_USB0_DDR_BRIDGE */ #define CLKID_MMC_PCLK 66 #define CLKID_DVIN 67 -#define CLKID_UART2 68 +/* CLKID_UART2 */ /* #define CLKID_SANA */ #define CLKID_VPU_INTR 70 #define CLKID_SEC_AHB_AHB3_BRIDGE 71 diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index a1b2b5088d3a..98b39c2e79af 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -17,6 +17,7 @@ #define CLKID_I2C 22 #define CLKID_SAR_ADC 23 #define CLKID_RNG0 25 +#define CLKID_UART0 26 #define CLKID_SPI 34 #define CLKID_ETH 36 #define CLKID_AIU_GLUE 38 @@ -24,12 +25,14 @@ #define CLKID_I2S_OUT 40 #define CLKID_MIXER_IFACE 44 #define CLKID_AIU 47 +#define CLKID_UART1 48 #define CLKID_USB0 50 #define CLKID_USB1 51 #define CLKID_USB 55 #define CLKID_HDMI_PCLK 63 #define CLKID_USB1_DDR_BRIDGE 64 #define CLKID_USB0_DDR_BRIDGE 65 +#define CLKID_UART2 68 #define CLKID_SANA 69 #define CLKID_GCLK_VENCI_INT0 77 #define CLKID_AOCLK_GATE 80 |