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| author | Ben Dooks <ben-linux@fluff.org> | 2009-10-28 19:34:23 +0100 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2009-10-28 19:34:23 +0100 |
| commit | 8e8821e5bbcfb177d1b00aa9888a85bc7d6bf3ae (patch) | |
| tree | eabad40564922b0faa767cdbcd55f55400c242a5 | |
| parent | ARM: S3C24XX: arch/arm/plat-s3c24xx: Move dereference after NULL test (diff) | |
| parent | ARM: S3C64XX: Set rate of crystal mux (diff) | |
| download | linux-8e8821e5bbcfb177d1b00aa9888a85bc7d6bf3ae.tar.xz linux-8e8821e5bbcfb177d1b00aa9888a85bc7d6bf3ae.zip | |
ARM: Merge fixes-s3c64xx
Merge branch 'fixes-s3c64xx' into fixes-s3c-2632-rc5
| -rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/regs-clock.h | 4 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/s3c6400-clock.c | 3 |
2 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index a8777a755dfa..ff46e7fa957a 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -51,8 +51,8 @@ #define S3C6400_CLKDIV0_HCLK_SHIFT (8) #define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) #define S3C6400_CLKDIV0_MPLL_SHIFT (4) -#define S3C6400_CLKDIV0_ARM_MASK (0x3 << 0) -#define S3C6410_CLKDIV0_ARM_MASK (0x7 << 0) +#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0) +#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0) #define S3C6400_CLKDIV0_ARM_SHIFT (0) /* CLKDIV1 */ diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index 9745852261e0..6ffa21eb1b91 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -677,6 +677,9 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); + /* For now assume the mux always selects the crystal */ + clk_ext_xtal_mux.parent = xtal_clk; + epll = s3c6400_get_epll(xtal); mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); |