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authorJesse Barnes <jbarnes@virtuousgeek.org>2010-10-19 22:07:57 +0200
committerJesse Barnes <jbarnes@virtuousgeek.org>2011-05-12 00:18:40 +0200
commitb48d4425b602f5f4978299474743dbea130d940d (patch)
tree7da23c264cab62bce753e60c4e8d5fbbb0aab0e7
parentPCI hotplug: acpiphp: assume device is in state D0 after powering on a slot. (diff)
downloadlinux-b48d4425b602f5f4978299474743dbea130d940d.tar.xz
linux-b48d4425b602f5f4978299474743dbea130d940d.zip
PCI: add ID-based ordering enable/disable support
Add support to allow drivers to enable/disable ID-based ordering. Where supported, ID-based ordering can significantly improve the latency of individual requests by preventing them from queueing up behind unrelated traffic. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
-rw-r--r--drivers/pci/pci.c53
-rw-r--r--include/linux/pci.h13
-rw-r--r--include/linux/pci_regs.h2
3 files changed, 68 insertions, 0 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 44d1c7c3876b..d0182bed7acc 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1834,6 +1834,59 @@ void pci_enable_ari(struct pci_dev *dev)
bridge->ari_enabled = 1;
}
+/**
+ * pci_enable_ido - enable ID-based ordering on a device
+ * @dev: the PCI device
+ * @type: which types of IDO to enable
+ *
+ * Enable ID-based ordering on @dev. @type can contain the bits
+ * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
+ * which types of transactions are allowed to be re-ordered.
+ */
+void pci_enable_ido(struct pci_dev *dev, unsigned long type)
+{
+ int pos;
+ u16 ctrl;
+
+ pos = pci_pcie_cap(dev);
+ if (!pos)
+ return;
+
+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
+ if (type & PCI_EXP_IDO_REQUEST)
+ ctrl |= PCI_EXP_IDO_REQ_EN;
+ if (type & PCI_EXP_IDO_COMPLETION)
+ ctrl |= PCI_EXP_IDO_CMP_EN;
+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
+}
+EXPORT_SYMBOL(pci_enable_ido);
+
+/**
+ * pci_disable_ido - disable ID-based ordering on a device
+ * @dev: the PCI device
+ * @type: which types of IDO to disable
+ */
+void pci_disable_ido(struct pci_dev *dev, unsigned long type)
+{
+ int pos;
+ u16 ctrl;
+
+ if (!pci_is_pcie(dev))
+ return;
+
+ pos = pci_pcie_cap(dev);
+ if (!pos)
+ return;
+
+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
+ if (type & PCI_EXP_IDO_REQUEST)
+ ctrl &= ~PCI_EXP_IDO_REQ_EN;
+ if (type & PCI_EXP_IDO_COMPLETION)
+ ctrl &= ~PCI_EXP_IDO_CMP_EN;
+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
+}
+EXPORT_SYMBOL(pci_disable_ido);
+
static int pci_acs_enable;
/**
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 96f70d7e058d..551ddcb5f940 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -828,6 +828,11 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
return __pci_enable_wake(dev, state, false, enable);
}
+#define PCI_EXP_IDO_REQUEST (1<<0)
+#define PCI_EXP_IDO_COMPLETION (1<<1)
+void pci_enable_ido(struct pci_dev *dev, unsigned long type);
+void pci_disable_ido(struct pci_dev *dev, unsigned long type);
+
/* For use by arch with custom probe code */
void set_pcie_port_type(struct pci_dev *pdev);
void set_pcie_hotplug_bridge(struct pci_dev *pdev);
@@ -1207,6 +1212,14 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
return 0;
}
+static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
+{
+}
+
+static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
+{
+}
+
static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
{
return -EIO;
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index be01380f798a..d9acf9b99814 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -510,6 +510,8 @@
#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
+#define PCI_EXP_IDO_REQ_EN 0x100 /* ID-based ordering request enable */
+#define PCI_EXP_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */