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authorLi Dongyang <dongyang.li@anu.edu.au>2016-12-03 01:53:17 +0100
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-12-06 10:54:33 +0100
commit817990ba1a1545875fed01a9014ac7f78dedf16d (patch)
tree8e9157ec764d161324353729e9d1a365a957dbef
parentstaging: lustre: llite: Add client mount opt to ignore suppress_pings (diff)
downloadlinux-817990ba1a1545875fed01a9014ac7f78dedf16d.tar.xz
linux-817990ba1a1545875fed01a9014ac7f78dedf16d.zip
staging: lustre: obdclass: limit lu_site hash table size on clients
Allocating a big hash table using the current formula does not really work for clients. We will create new hash table for each mount on a single client which is a lot of memory more than expected. This patch limits the hash table up to 8M for clients, which has 524288 entries. Signed-off-by: Li Dongyang <dongyang.li@anu.edu.au> Intel-bug-id: https://jira.hpdd.intel.com/browse/LU-7689 Reviewed-on: http://review.whamcloud.com/18048 Reviewed-by: Fan Yong <fan.yong@intel.com> Reviewed-by: Alex Zhuravlev <alexey.zhuravlev@intel.com> Reviewed-by: Oleg Drokin <oleg.drokin@intel.com> Signed-off-by: James Simmons <jsimmons@infradead.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/staging/lustre/lustre/obdclass/lu_object.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/staging/lustre/lustre/obdclass/lu_object.c b/drivers/staging/lustre/lustre/obdclass/lu_object.c
index a02aaa3a3b37..80e09846e3be 100644
--- a/drivers/staging/lustre/lustre/obdclass/lu_object.c
+++ b/drivers/staging/lustre/lustre/obdclass/lu_object.c
@@ -68,6 +68,7 @@ enum {
#define LU_SITE_BITS_MIN 12
#define LU_SITE_BITS_MAX 24
+#define LU_SITE_BITS_MAX_CL 19
/**
* total 256 buckets, we don't want too many buckets because:
* - consume too much memory
@@ -878,6 +879,9 @@ static unsigned long lu_htable_order(struct lu_device *top)
unsigned long cache_size;
unsigned long bits;
+ if (!strcmp(top->ld_type->ldt_name, LUSTRE_VVP_NAME))
+ bits_max = LU_SITE_BITS_MAX_CL;
+
/*
* Calculate hash table size, assuming that we want reasonable
* performance when 20% of total memory is occupied by cache of