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authorStephen Warren <swarren@nvidia.com>2012-02-14 21:39:39 +0100
committerOlof Johansson <olof@lixom.net>2012-02-26 23:24:51 +0100
commitf35b431dde39fb40944d1024f08d88fbf04a3193 (patch)
tree5a8f1dbb1e82cbfa5a50db981e1e68580f1b598d
parentARM: tegra: paz00: fix wrong UART port on mini-pcie plug (diff)
downloadlinux-f35b431dde39fb40944d1024f08d88fbf04a3193.tar.xz
linux-f35b431dde39fb40944d1024f08d88fbf04a3193.zip
ARM: tegra: select required CPU and L2 errata options
The ARM IP revisions in Tegra are: Tegra20: CPU r1p1, PL310 r2p0 Tegra30: CPU A01=r2p7/>=A02=r2p9, NEON r2p3-50, PL310 r3p1-50 Based on work by Olof Johansson, although the actual list of errata is somewhat different here, since I added a bunch more and removed one PL310 erratum that doesn't seem applicable. Signed-off-by: Stephen Warren <swarren@nvidia.com> Cc: stable@vger.kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r--arch/arm/mach-tegra/Kconfig12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 373652d76b90..46b6839e5b28 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -10,6 +10,13 @@ config ARCH_TEGRA_2x_SOC
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ULPI if USB_SUPPORT
select USB_ULPI_VIEWPORT if USB_SUPPORT
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_742230
+ select ARM_ERRATA_751472
+ select ARM_ERRATA_754327
+ select ARM_ERRATA_764369
+ select PL310_ERRATA_727915 if CACHE_L2X0
+ select PL310_ERRATA_769419 if CACHE_L2X0
help
Support for NVIDIA Tegra AP20 and T20 processors, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -23,6 +30,11 @@ config ARCH_TEGRA_3x_SOC
select USB_ULPI if USB_SUPPORT
select USB_ULPI_VIEWPORT if USB_SUPPORT
select USE_OF
+ select ARM_ERRATA_743622
+ select ARM_ERRATA_751472
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_764369
+ select PL310_ERRATA_769419 if CACHE_L2X0
help
Support for NVIDIA Tegra T30 processor family, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller