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authorBharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>2016-08-30 12:39:17 +0200
committerBjorn Helgaas <bhelgaas@google.com>2016-09-13 17:15:41 +0200
commitf665bd1515aceb80990fdbc91b7c8aed045f5da8 (patch)
tree9125a40e2fbed4a22a9e0951859585aaa4a6ca32
parentPCI: xilinx-nwl: Expand error logging (diff)
downloadlinux-f665bd1515aceb80990fdbc91b7c8aed045f5da8.tar.xz
linux-f665bd1515aceb80990fdbc91b7c8aed045f5da8.zip
PCI: xilinx-nwl: Enable all MSI interrupts using MSI mask
The current mask enables and allows only one MSI interrupt on each MSI line. Enable all MSI interrupts, which will also support Endpoints with multi-MSI support. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--drivers/pci/host/pcie-xilinx-nwl.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
index dfdf58f20b19..07261a7f4627 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -120,8 +120,8 @@
MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
/* MSI interrupt status mask bits */
-#define MSGF_MSI_SR_LO_MASK BIT(0)
-#define MSGF_MSI_SR_HI_MASK BIT(0)
+#define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
+#define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
#define MSII_PRESENT BIT(0)
#define MSII_ENABLE BIT(0)