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authorJinbum Park <jinb.park7@gmail.com>2017-12-12 01:20:51 +0100
committerRussell King <rmk+kernel@armlinux.org.uk>2017-12-17 23:16:20 +0100
commit670431eaacbfa30be59f4ea027a2d9662ddf2bff (patch)
tree984f7808115c400fb3aeaebcfb306f3ecc505ad1
parentARM: 8732/1: NOMMU: Allow userspace to access background MPU region (diff)
downloadlinux-670431eaacbfa30be59f4ea027a2d9662ddf2bff.tar.xz
linux-670431eaacbfa30be59f4ea027a2d9662ddf2bff.zip
ARM: 8733/1: hw_breakpoint: Mark variables as __ro_after_init
core_num_brps, core_num_wrps, debug_arch, has_ossr, max_watchpoint_len are setup once while init stage, and never changed after that. so it is good candidate for __ro_after_init. Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Jinbum Park <jinb.park7@gmail.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
-rw-r--r--arch/arm/kernel/hw_breakpoint.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index af2a7f1e3103..629e25152c0d 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -44,17 +44,17 @@ static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
/* Number of BRP/WRP registers on this CPU. */
-static int core_num_brps;
-static int core_num_wrps;
+static int core_num_brps __ro_after_init;
+static int core_num_wrps __ro_after_init;
/* Debug architecture version. */
-static u8 debug_arch;
+static u8 debug_arch __ro_after_init;
/* Does debug architecture support OS Save and Restore? */
-static bool has_ossr;
+static bool has_ossr __ro_after_init;
/* Maximum supported watchpoint length. */
-static u8 max_watchpoint_len;
+static u8 max_watchpoint_len __ro_after_init;
#define READ_WB_REG_CASE(OP2, M, VAL) \
case ((OP2 << 4) + M): \