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| author | Stephen Boyd <sboyd@kernel.org> | 2018-05-01 23:44:16 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-05-01 23:44:16 +0200 |
| commit | c964cfc612b59910593fa10ee1c2673db274c9c7 (patch) | |
| tree | 4bf48c00b9cff523de11be6be2f459ffafa552a4 | |
| parent | clk: meson: honor CLK_MUX_ROUND_CLOSEST in clk_regmap (diff) | |
| parent | clk: meson: meson8b: fix meson8b_cpu_clk parent clock name (diff) | |
| download | linux-c964cfc612b59910593fa10ee1c2673db274c9c7.tar.xz linux-c964cfc612b59910593fa10ee1c2673db274c9c7.zip | |
Merge tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson into clk-fixes
Pull meson clk fixes from Jerome Brunet:
- fix typos in two meson8 clock names
- remove unused clock ops declaration
* tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson:
clk: meson: meson8b: fix meson8b_cpu_clk parent clock name
clk: meson: meson8b: fix meson8b_fclk_div3_div clock name
clk: meson: drop meson_aoclk_gate_regmap_ops
| -rw-r--r-- | drivers/clk/meson/gxbb-aoclk.h | 2 | ||||
| -rw-r--r-- | drivers/clk/meson/meson8b.c | 5 |
2 files changed, 3 insertions, 4 deletions
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h index 0be78383f257..badc4c22b4ee 100644 --- a/drivers/clk/meson/gxbb-aoclk.h +++ b/drivers/clk/meson/gxbb-aoclk.h @@ -17,8 +17,6 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 -extern const struct clk_ops meson_aoclk_gate_regmap_ops; - struct aoclk_cec_32k { struct clk_hw hw; struct regmap *regmap; diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index cc2992493e0b..d0524ec71aad 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -253,7 +253,7 @@ static struct clk_fixed_factor meson8b_fclk_div3_div = { .mult = 1, .div = 3, .hw.init = &(struct clk_init_data){ - .name = "fclk_div_div3", + .name = "fclk_div3_div", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, @@ -632,7 +632,8 @@ static struct clk_regmap meson8b_cpu_clk = { .hw.init = &(struct clk_init_data){ .name = "cpu_clk", .ops = &clk_regmap_mux_ro_ops, - .parent_names = (const char *[]){ "xtal", "cpu_out_sel" }, + .parent_names = (const char *[]){ "xtal", + "cpu_scale_out_sel" }, .num_parents = 2, .flags = (CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), |