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| author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-08-27 04:19:54 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-08-30 19:56:45 +0200 |
| commit | 116389ed21e4ad88f65e7ec5ed6ca224acb89115 (patch) | |
| tree | 2e891ce607811b12b8be1ab1c9d69a3a2e3b98c1 | |
| parent | i7300_edac: add global error registers (diff) | |
| download | linux-116389ed21e4ad88f65e7ec5ed6ca224acb89115.tar.xz linux-116389ed21e4ad88f65e7ec5ed6ca224acb89115.zip | |
i7300_edac: Add a FIXME note about the error correction type
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
| -rw-r--r-- | drivers/edac/i7300_edac.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c index 7e035b6d0d0f..36265e21fef2 100644 --- a/drivers/edac/i7300_edac.c +++ b/drivers/edac/i7300_edac.c @@ -841,6 +841,15 @@ static int decode_mtr(struct i7300_pvt *pvt, p_csrow->grain = 8; p_csrow->nr_pages = dinfo->megabytes << 8; p_csrow->mtype = MEM_FB_DDR2; + + /* + * FIXME: the type of error detection actually depends of the + * mode of operation. When it is just one single memory chip, at + * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code. + * In normal or mirrored mode, it uses Single Device Data correction, + * with the possibility of using an extended algorithm for x8 memories + * See datasheet Sections 7.3.6 to 7.3.8 + */ p_csrow->edac_mode = EDAC_S8ECD8ED; /* ask what device type on this row */ |