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| author | Andi Kleen <ak@suse.de> | 2006-01-11 22:46:36 +0100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-12 04:05:02 +0100 |
| commit | dd52d642db8ca05267456a07a592922e8b093e1c (patch) | |
| tree | 325cbfbe911c806a8aefb04f5b0c3a5d90d06c94 | |
| parent | [PATCH] i386: Move phys_proc_id/early intel workaround to correct function. (diff) | |
| download | linux-dd52d642db8ca05267456a07a592922e8b093e1c.tar.xz linux-dd52d642db8ca05267456a07a592922e8b093e1c.zip | |
[PATCH] x86_64: Remove unused AMD K8 C stepping flag
X86_FEATURE_K8_C was a synthetic Linux CPUID flag that was used for some
code optimizations in Opteron C stepping or later. But support for pre C
stepping optimizations has been removed, so this isn't needed anymore.
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
| -rw-r--r-- | arch/x86_64/kernel/setup.c | 6 | ||||
| -rw-r--r-- | include/asm-x86_64/cpufeature.h | 2 |
2 files changed, 1 insertions, 7 deletions
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c index 173bdc55113b..a5ebd03ecbd1 100644 --- a/arch/x86_64/kernel/setup.c +++ b/arch/x86_64/kernel/setup.c @@ -879,7 +879,6 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c) static int __init init_amd(struct cpuinfo_x86 *c) { int r; - int level; #ifdef CONFIG_SMP unsigned long value; @@ -902,11 +901,6 @@ static int __init init_amd(struct cpuinfo_x86 *c) 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ clear_bit(0*32+31, &c->x86_capability); - /* C-stepping K8? */ - level = cpuid_eax(1); - if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) - set_bit(X86_FEATURE_K8_C, &c->x86_capability); - r = get_model_name(c); if (!r) { switch (c->x86) { diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86_64/cpufeature.h index 72b39f514798..41c0ac8559be 100644 --- a/include/asm-x86_64/cpufeature.h +++ b/include/asm-x86_64/cpufeature.h @@ -61,7 +61,7 @@ #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ -#define X86_FEATURE_K8_C (3*32+ 4) /* C stepping K8 */ +/* 4 free */ #define X86_FEATURE_CONSTANT_TSC (3*32+5) /* TSC runs at constant rate */ #define X86_FEATURE_SYNC_RDTSC (3*32+6) /* RDTSC syncs CPU core */ |