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authorStephen Boyd <sboyd@codeaurora.org>2016-08-19 01:41:05 +0200
committerStephen Boyd <sboyd@codeaurora.org>2016-08-19 01:41:05 +0200
commit91d17dc341795731794b7284f6f32f07ebdd7a86 (patch)
tree56d341e50e31b94f0443d024f90a6d7c4b0c0d11
parentclk: berlin: Migrate to clk_hw based registration and OF APIs (diff)
parentclk: renesas: r8a7796: Add watchdog module clock (diff)
downloadlinux-91d17dc341795731794b7284f6f32f07ebdd7a86.tar.xz
linux-91d17dc341795731794b7284f6f32f07ebdd7a86.zip
Merge tag 'clk-renesas-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Merge r8a7796 watchdog clk support from Geert Uytterhoeven: Add all clocks related to the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC. * tag 'clk-renesas-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add watchdog module clock clk: renesas: r8a7796: Add watchdog core clocks
-rw-r--r--drivers/clk/renesas/r8a7796-cpg-mssr.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index c84b549c14d2..c0dee762ed23 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -45,6 +45,7 @@ enum clk_ids {
CLK_S3,
CLK_SDSRC,
CLK_SSPSRC,
+ CLK_RINT,
/* Module Clocks */
MOD_CLK_BASE
@@ -94,10 +95,16 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
+
+ DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
+ DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
+
+ DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
+ DEF_MOD("rwdt0", 402, R8A7796_CLK_R),
DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
};