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authorJiang Liu <jiang.liu@huawei.com>2012-07-24 11:20:31 +0200
committerBjorn Helgaas <bhelgaas@google.com>2012-08-23 18:11:16 +0200
commit5cdaaf8a11ba34fb08877bc1982d6d54b29bb8f4 (patch)
tree75ede29350e887a6c589d43836eb39a525363a88
parentdrm/radeon: Use PCI Express Capability accessors (diff)
downloadlinux-5cdaaf8a11ba34fb08877bc1982d6d54b29bb8f4.tar.xz
linux-5cdaaf8a11ba34fb08877bc1982d6d54b29bb8f4.zip
rapdio/tsi721: Use PCI Express Capability accessors
Use PCI Express Capability access functions to simplify tsi721 driver. [bhelgaas: use word (16-bit) accesses for PCI_EXP_DEVCTL, PCI_EXP_DEVCTL2] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alexandre Bounine <alexandre.bounine@idt.com>
-rw-r--r--drivers/rapidio/devices/tsi721.c19
1 files changed, 7 insertions, 12 deletions
diff --git a/drivers/rapidio/devices/tsi721.c b/drivers/rapidio/devices/tsi721.c
index 722246cf20ab..fc22b93e0924 100644
--- a/drivers/rapidio/devices/tsi721.c
+++ b/drivers/rapidio/devices/tsi721.c
@@ -2212,9 +2212,8 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct tsi721_device *priv;
- int i, cap;
+ int i;
int err;
- u32 regval;
priv = kzalloc(sizeof(struct tsi721_device), GFP_KERNEL);
if (priv == NULL) {
@@ -2320,20 +2319,16 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
}
- cap = pci_pcie_cap(pdev);
- BUG_ON(cap == 0);
+ BUG_ON(!pci_is_pcie(pdev));
/* Clear "no snoop" and "relaxed ordering" bits, use default MRRS. */
- pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, &regval);
- regval &= ~(PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN |
- PCI_EXP_DEVCTL_NOSNOOP_EN);
- regval |= 0x2 << MAX_READ_REQUEST_SZ_SHIFT;
- pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL, regval);
+ pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
+ PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN |
+ PCI_EXP_DEVCTL_NOSNOOP_EN,
+ 0x2 << MAX_READ_REQUEST_SZ_SHIFT);
/* Adjust PCIe completion timeout. */
- pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL2, &regval);
- regval &= ~(0x0f);
- pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL2, regval | 0x2);
+ pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL2, 0xf, 0x2);
/*
* FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block