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authorAlex Deucher <alexander.deucher@amd.com>2014-11-07 18:00:25 +0100
committerAlex Deucher <alexander.deucher@amd.com>2014-11-12 17:56:38 +0100
commit9feb3dda5ce0a9d2155f20506384d2e359f151ce (patch)
tree67afb01dd0b52c2ec37d7defedf515efa0c7049c
parentdrm/radeon/ci: handle gpio controlled dpm features properly (diff)
downloadlinux-9feb3dda5ce0a9d2155f20506384d2e359f151ce.tar.xz
linux-9feb3dda5ce0a9d2155f20506384d2e359f151ce.zip
drm/radeon: fix for memory training on bonaire 0x6649
Workaround for memory link training on certain variants of 0x6649. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/radeon/cik.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 377afa504d2b..57a359d34830 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1806,7 +1806,7 @@ int ci_mc_load_microcode(struct radeon_device *rdev)
{
const __be32 *fw_data = NULL;
const __le32 *new_fw_data = NULL;
- u32 running, blackout = 0;
+ u32 running, blackout = 0, tmp;
u32 *io_mc_regs = NULL;
const __le32 *new_io_mc_regs = NULL;
int i, regs_size, ucode_size;
@@ -1866,6 +1866,15 @@ int ci_mc_load_microcode(struct radeon_device *rdev)
WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
}
}
+
+ tmp = RREG32(MC_SEQ_MISC0);
+ if ((rdev->pdev->device == 0x6649) && ((tmp & 0xff00) == 0x5600)) {
+ WREG32(MC_SEQ_IO_DEBUG_INDEX, 5);
+ WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023);
+ WREG32(MC_SEQ_IO_DEBUG_INDEX, 9);
+ WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0);
+ }
+
/* load the MC ucode */
for (i = 0; i < ucode_size; i++) {
if (rdev->new_fw)