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| author | FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> | 2010-06-30 04:10:08 +0200 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2010-07-06 19:42:04 +0200 |
| commit | c6673cb54d191dd42935a61fcb0c452a4753fb23 (patch) | |
| tree | 2ed6efb2cea2b11851f75738c5307f685361328c | |
| parent | tile: remove homegrown L1_CACHE_ALIGN macro (diff) | |
| download | linux-c6673cb54d191dd42935a61fcb0c452a4753fb23.tar.xz linux-c6673cb54d191dd42935a61fcb0c452a4753fb23.zip | |
tile: set ARCH_KMALLOC_MINALIGN
Architectures that handle DMA-non-coherent memory need to set
ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is DMA-safe:
the buffer doesn't share a cache with the others.
Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: Chris Metcalf <cmetcalf@tilera.com>
| -rw-r--r-- | arch/tile/include/asm/cache.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index ee597147e5cd..869a14f4ceae 100644 --- a/arch/tile/include/asm/cache.h +++ b/arch/tile/include/asm/cache.h @@ -31,6 +31,14 @@ #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES) +/* + * TILE-Gx is fully coherents so we don't need to define + * ARCH_KMALLOC_MINALIGN. + */ +#ifndef __tilegx__ +#define ARCH_KMALLOC_MINALIGN L2_CACHE_BYTES +#endif + /* use the cache line size for the L2, which is where it counts */ #define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT #define SMP_CACHE_BYTES L2_CACHE_BYTES |