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| author | Will Deacon <will.deacon@arm.com> | 2018-12-13 16:34:44 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-12-13 16:34:44 +0100 |
| commit | 26a25c841d9e6ba4ceba4b8d7ce3f3227f7510ce (patch) | |
| tree | ec8589936bb72ff721ddcb37cc9682fc572ce3d4 | |
| parent | arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 field (diff) | |
| download | linux-26a25c841d9e6ba4ceba4b8d7ce3f3227f7510ce.tar.xz linux-26a25c841d9e6ba4ceba4b8d7ce3f3227f7510ce.zip | |
arm64: perf: Treat EXCLUDE_EL* bit definitions as unsigned
Although the upper 32 bits of the PMEVTYPER<n>_EL0 registers are RES0,
we should treat the EXCLUDE_EL* bit definitions as unsigned so that we
avoid accidentally sign-extending the privilege filtering bit (bit 31)
into the upper half of the register.
Signed-off-by: Will Deacon <will.deacon@arm.com>
| -rw-r--r-- | arch/arm64/include/asm/perf_event.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h index c63e5e4fdccd..c593761ba61c 100644 --- a/arch/arm64/include/asm/perf_event.h +++ b/arch/arm64/include/asm/perf_event.h @@ -206,9 +206,9 @@ /* * Event filters for PMUv3 */ -#define ARMV8_PMU_EXCLUDE_EL1 (1 << 31) -#define ARMV8_PMU_EXCLUDE_EL0 (1 << 30) -#define ARMV8_PMU_INCLUDE_EL2 (1 << 27) +#define ARMV8_PMU_EXCLUDE_EL1 (1U << 31) +#define ARMV8_PMU_EXCLUDE_EL0 (1U << 30) +#define ARMV8_PMU_INCLUDE_EL2 (1U << 27) /* * PMUSERENR: user enable reg |