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authorMans Rullgard <mans@mansr.com>2015-10-02 18:50:31 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2015-10-04 20:16:12 +0200
commit3c5a0357fdb3a9116a48dbdb0abb91fd23fbff80 (patch)
treed2542ecf101ff6bef3b72cf72ff4cf8b3506bee9
parenttty: fix data race on tty_buffer.commit (diff)
downloadlinux-3c5a0357fdb3a9116a48dbdb0abb91fd23fbff80.tar.xz
linux-3c5a0357fdb3a9116a48dbdb0abb91fd23fbff80.zip
serial: 8250: add uart_config entry for PORT_RT2880
This adds an entry to the uart_config table for PORT_RT2880 enabling rx/tx FIFOs. The UART is actually a Palmchip BK-3103 which is found in several devices from Alchemy/RMI, Ralink, and Sigma Designs. Signed-off-by: Mans Rullgard <mans@mansr.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/tty/serial/8250/8250_port.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index b1e0ba3e525b..0bbf34035d6a 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -261,6 +261,14 @@ configured less than Maximum supported fifo bytes */
UART_FCR7_64BYTE,
.flags = UART_CAP_FIFO,
},
+ [PORT_RT2880] = {
+ .name = "Palmchip BK-3103",
+ .fifo_size = 16,
+ .tx_loadsz = 16,
+ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+ .rxtrig_bytes = {1, 4, 8, 14},
+ .flags = UART_CAP_FIFO,
+ },
};
/* Uart divisor latch read */