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authorRoger Quadros <rogerq@ti.com>2016-03-03 12:28:20 +0100
committerTony Lindgren <tony@atomide.com>2016-04-12 23:32:02 +0200
commit91d075c7cf2cf621142c0a69f2acc690b81cb8a2 (patch)
tree7a76ea05943023f22d3927f54b62cdafd496196d
parentARM: dts: dra7-evm: Add missing regulators (diff)
downloadlinux-91d075c7cf2cf621142c0a69f2acc690b81cb8a2.tar.xz
linux-91d075c7cf2cf621142c0a69f2acc690b81cb8a2.zip
ARM: dts: dra7-evm: Fix comment about NAND configuration
The switch configuration for NAND is actually the other way round. Also mention ON/OFF states as that is more natural to understand (without the help of schematics) when compared to HIGH/LOW. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 6e61cfa12326..05c135d84374 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -256,8 +256,9 @@
nand_flash_x16: nand_flash_x16 {
/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
* So NAND flash requires following switch settings:
- * SW5.9 (GPMC_WPN) = LOW
- * SW5.1 (NAND_BOOTn) = HIGH */
+ * SW5.1 (NAND_BOOTn) = ON (LOW)
+ * SW5.9 (GPMC_WPN) = OFF (HIGH)
+ */
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */