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| author | Emilio López <emilio@elopez.com.ar> | 2014-03-19 19:19:31 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-04-14 11:58:39 +0200 |
| commit | 04ebcb5405105d9b9bd9633d74e87e0979bddc55 (patch) | |
| tree | 90fe73a609544ab44749d3ad0efcc140373c94ef | |
| parent | Linux 3.15-rc1 (diff) | |
| download | linux-04ebcb5405105d9b9bd9633d74e87e0979bddc55.tar.xz linux-04ebcb5405105d9b9bd9633d74e87e0979bddc55.zip | |
ARM: sun7i: fix PLL4 clock and add PLL8
Allwinner reworked the PLL4 clock in sun7i; so we need to change the
compatible. Additionally, PLL8 is compatible with this new PLL4
implementation, so let's add a node for it as well.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| -rw-r--r-- | arch/arm/boot/dts/sun7i-a20.dtsi | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 32efc105df83..c4f665f1b793 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -87,7 +87,7 @@ pll4: clk@01c20018 { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; + compatible = "allwinner,sun7i-a20-pll4-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; clock-output-names = "pll4"; @@ -109,6 +109,14 @@ clock-output-names = "pll6_sata", "pll6_other", "pll6"; }; + pll8: clk@01c20040 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-pll4-clk"; + reg = <0x01c20040 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll8"; + }; + cpu: cpu@01c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-cpu-clk"; |