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authorAndrew Jeffery <andrew@aj.id.au>2016-12-20 08:15:34 +0100
committerLee Jones <lee.jones@linaro.org>2017-02-13 10:29:42 +0100
commit73bee1d330a80943f1d0e13d32a739b80e44a470 (patch)
tree0b1e9cfe0490dda0e7d9b6028d57921fb4150cd1
parentmfd: dt: Add Aspeed Low Pin Count Controller bindings (diff)
downloadlinux-73bee1d330a80943f1d0e13d32a739b80e44a470.tar.xz
linux-73bee1d330a80943f1d0e13d32a739b80e44a470.zip
mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)
The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends on bits in both the System Control Unit and the LPC Host Controller. The Aspeed LPC Host Controller is described as a child node of the LPC host-range syscon device for arbitration of access by the host controller and pinmux drivers. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/mfd/aspeed-lpc.txt26
1 files changed, 26 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
index a97131aba446..514d82ced95b 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
@@ -109,3 +109,29 @@ lpc: lpc@1e789000 {
};
};
+Host Node Children
+==================
+
+LPC Host Controller
+-------------------
+
+The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
+between the host and the baseboard management controller. The registers exist
+in the "host" portion of the Aspeed LPC controller, which must be the parent of
+the LPC host controller node.
+
+Required properties:
+
+- compatible: One of:
+ "aspeed,ast2400-lhc";
+ "aspeed,ast2500-lhc";
+
+- reg: contains offset/length values of the LHC memory regions. In the
+ AST2400 and AST2500 there are two regions.
+
+Example:
+
+lhc: lhc@20 {
+ compatible = "aspeed,ast2500-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
+};