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| author | Marc Zyngier <marc.zyngier@arm.com> | 2013-04-12 15:00:16 +0200 |
|---|---|---|
| committer | Christoffer Dall <cdall@cs.columbia.edu> | 2013-04-17 01:21:25 +0200 |
| commit | 865499ea90d399e0682bcce3ae7af24277633699 (patch) | |
| tree | 4f43ed01655ccf1241187da59c8c0cee44f26558 | |
| parent | ARM: KVM: fix KVM_CAP_ARM_SET_DEVICE_ADDR reporting (diff) | |
| download | linux-865499ea90d399e0682bcce3ae7af24277633699.tar.xz linux-865499ea90d399e0682bcce3ae7af24277633699.zip | |
ARM: KVM: fix L_PTE_S2_RDWR to actually be Read/Write
Looks like our L_PTE_S2_RDWR definition is slightly wrong,
and is actually write only (see ARM ARM Table B3-9, Stage 2 control
of access permissions). Didn't make a difference for normal pages,
as we OR the flags together, but I'm still wondering how it worked
for Stage-2 mapped devices, such as the GIC.
Brown paper bag time, again.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
| -rw-r--r-- | arch/arm/include/asm/pgtable-3level.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index 6ef8afd1b64c..86b8fe398b95 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -111,7 +111,7 @@ #define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */ #define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */ #define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */ -#define L_PTE_S2_RDWR (_AT(pteval_t, 2) << 6) /* HAP[2:1] */ +#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */ /* * Hyp-mode PL2 PTE definitions for LPAE. |