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| author | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2015-03-17 17:33:54 +0100 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2015-03-19 11:07:47 +0100 |
| commit | 292a3546b9eb20bf5a292f4e55dd1a027424669f (patch) | |
| tree | 86a3651ede92225bbbbd6e6819263b584efde379 | |
| parent | ARM: mvebu: clk: remove cpuclk resources overlapping coredivclk registers on ... (diff) | |
| download | linux-292a3546b9eb20bf5a292f4e55dd1a027424669f.tar.xz linux-292a3546b9eb20bf5a292f4e55dd1a027424669f.zip | |
ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level
For L2 cache controller node, cache-level property is mandatory. Let's
add it to Armada 370 and Armada XP device tree.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
| -rw-r--r-- | arch/arm/boot/dts/armada-370.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/armada-xp.dtsi | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 50f259b20f94..00b50db57c9c 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -129,6 +129,7 @@ compatible = "marvell,aurora-outer-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; + cache-level = <2>; cache-unified; wt-override; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 448af3352175..013d63f69e36 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -79,6 +79,7 @@ compatible = "marvell,aurora-system-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; + cache-level = <2>; cache-unified; wt-override; }; |