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authorNeil Armstrong <narmstrong@baylibre.com>2019-06-25 14:36:47 +0200
committerKevin Hilman <khilman@baylibre.com>2019-08-05 23:06:55 +0200
commit3d4bacdc207a7b62941700b374e7199cbb184a43 (patch)
treec5257cd2f19a7e1c06522ca8390e9c3b78f81c05
parentLinus 5.3-rc1 (diff)
downloadlinux-3d4bacdc207a7b62941700b374e7199cbb184a43.tar.xz
linux-3d4bacdc207a7b62941700b374e7199cbb184a43.zip
arm64: dts: meson-g12a: add missing dwc2 phy-names
The G12A USB2 OTG capable PHY uses a 8bit large UTMI bus, and the OTG controller gets the PHY but width by probing the associated phy. By default it will use 16bit wide settings if a phy is not specified, in our case we specified the phy, but not the phy-names. The dwc2 bindings specifies that if phys is present, phy-names shall be "usb2-phy". Adding phy-names = "usb2-phy" solves the OTG PHY bus configuration. Fixes: 9baf7d6be730 ("arm64: dts: meson: g12a: Add G12A USB nodes") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-g12a.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index f8d43e3dcf20..1785552d450c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -2386,6 +2386,7 @@
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
clock-names = "ddr";
phys = <&usb2_phy1>;
+ phy-names = "usb2-phy";
dr_mode = "peripheral";
g-rx-fifo-size = <192>;
g-np-tx-fifo-size = <128>;