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authorEric Yang <Eric.Yang2@amd.com>2019-11-15 18:04:25 +0100
committerAlex Deucher <alexander.deucher@amd.com>2019-12-06 00:23:04 +0100
commit44ce6c3dc8479bb3ed68df13b502b0901675e7d6 (patch)
tree45979ce66d0ea9908ce127875dd62ff3e61d781b
parentdrm/amd/display: Fix screen tearing on vrr tests (diff)
downloadlinux-44ce6c3dc8479bb3ed68df13b502b0901675e7d6.tar.xz
linux-44ce6c3dc8479bb3ed68df13b502b0901675e7d6.zip
drm/amd/display: update dispclk and dppclk vco frequency
Value obtained from DV is not allowing 8k60 CTA mode with DSC to pass, after checking real value being used in hw, find out that correct value is 3600, which will allow that mode. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 6d99b4760695..c28cb5d50cf4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -257,7 +257,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.vmm_page_size_bytes = 4096,
.dram_clock_change_latency_us = 23.84,
.return_bus_width_bytes = 64,
- .dispclk_dppclk_vco_speed_mhz = 3550,
+ .dispclk_dppclk_vco_speed_mhz = 3600,
.xfc_bus_transport_time_us = 4,
.xfc_xbuf_latency_tolerance_us = 4,
.use_urgent_burst_bw = 1,