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| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2011-12-23 09:30:47 +0100 |
|---|---|---|
| committer | Marek Szyprowski <m.szyprowski@samsung.com> | 2012-03-28 16:36:43 +0200 |
| commit | 8a4134322bd429d24f71147eb59a47a981e8f63a (patch) | |
| tree | bce9920c5f163669666693cd9d307bd865ad2bb1 | |
| parent | common: dma-mapping: introduce mmap method (diff) | |
| download | linux-8a4134322bd429d24f71147eb59a47a981e8f63a.tar.xz linux-8a4134322bd429d24f71147eb59a47a981e8f63a.zip | |
common: DMA-mapping: add WRITE_COMBINE attribute
DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
buffered to improve performance. It will be used by the replacement for
ARM/ARV32 specific dma_alloc_writecombine() function.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | Documentation/DMA-attributes.txt | 10 | ||||
| -rw-r--r-- | include/linux/dma-attrs.h | 1 |
2 files changed, 11 insertions, 0 deletions
diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txt index b768cc0e402b..811a5d458dae 100644 --- a/Documentation/DMA-attributes.txt +++ b/Documentation/DMA-attributes.txt @@ -31,3 +31,13 @@ may be weakly ordered, that is that reads and writes may pass each other. Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING, those that do not will simply ignore the attribute and exhibit default behavior. + +DMA_ATTR_WRITE_COMBINE +---------------------- + +DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be +buffered to improve performance. + +Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE, +those that do not will simply ignore the attribute and exhibit default +behavior. diff --git a/include/linux/dma-attrs.h b/include/linux/dma-attrs.h index 71ad34eca6e3..ada61e1abf29 100644 --- a/include/linux/dma-attrs.h +++ b/include/linux/dma-attrs.h @@ -13,6 +13,7 @@ enum dma_attr { DMA_ATTR_WRITE_BARRIER, DMA_ATTR_WEAK_ORDERING, + DMA_ATTR_WRITE_COMBINE, DMA_ATTR_MAX, }; |