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authorMichael Ellerman <michael@ellerman.id.au>2011-04-07 23:22:23 +0200
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-04-27 06:18:48 +0200
commita7b8ad405862fb10e496ce839d423dfc94ac821b (patch)
tree555b32f7672568650556a81fcc34d3ef27a52e3c
parentpowerpc: Use MSR_64BIT in sstep.c, fix kprobes on BOOK3E (diff)
downloadlinux-a7b8ad405862fb10e496ce839d423dfc94ac821b.tar.xz
linux-a7b8ad405862fb10e496ce839d423dfc94ac821b.zip
powerpc/book3e: Fix extlb size
The calculation of the size for the exception save area of the TLB miss handler is wrong, luckily it's too big not too small. Rework it to make it a bit clearer, and also correct. We want 3 save areas, each EX_TLB_SIZE _bytes_. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-rw-r--r--arch/powerpc/include/asm/paca.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index f6da4f517fca..65c13c48db43 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -106,7 +106,8 @@ struct paca_struct {
pgd_t *pgd; /* Current PGD */
pgd_t *kernel_pgd; /* Kernel PGD */
u64 exgen[8] __attribute__((aligned(0x80)));
- u64 extlb[EX_TLB_SIZE*3] __attribute__((aligned(0x80)));
+ /* We can have up to 3 levels of reentrancy in the TLB miss handler */
+ u64 extlb[3][EX_TLB_SIZE / sizeof(u64)] __attribute__((aligned(0x80)));
u64 exmc[8]; /* used for machine checks */
u64 excrit[8]; /* used for crit interrupts */
u64 exdbg[8]; /* used for debug interrupts */