diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2015-02-11 20:23:13 +0100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2015-02-11 20:23:13 +0100 |
| commit | ce01e871a1d44cc97cdd7e5ba6cb0c3613c15552 (patch) | |
| tree | f1f3c8a0022d34d3da54700b0e48a1d7be48fe50 | |
| parent | Merge tag 'gpio-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/lin... (diff) | |
| parent | sh-pfc: emev2 - Fix mangled author name (diff) | |
| download | linux-ce01e871a1d44cc97cdd7e5ba6cb0c3613c15552.tar.xz linux-ce01e871a1d44cc97cdd7e5ba6cb0c3613c15552.zip | |
Merge tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pincontrol updates from Linus Walleij:
:This is the bulk of pin control changes for the v3.20 cycle:
Framework changes and enhancements:
- Passing -DDEBUG recursively to subdir drivers so we get debug
messages properly turned on.
- Infer map type from DT property in the groups parsing code in the
generic pinconfig code.
- Support for custom parameter passing in generic pin config. This
is used when you are using the generic pin config, but want to add
a few custom properties that no other driver will use.
New drivers:
- Driver for the Xilinx Zynq
- Driver for the AmLogic Meson SoCs
New features in drivers:
- Sleep support (suspend/resume) for the Cherryview driver
- mvebeu a38x can now mux a UART on pins MPP19 and MPP20
- Migrated the qualcomm driver to generic pin config handling of
extended config options in the core code.
- Support BUS1 and AUDIO in the Exynos pin controller.
- Add some missing functions in the sun6i driver.
- Add support for the A31S variant in the sun6i driver.
- EMEv2 support in the Renesas PFC driver.
- Add support for Qualcomm MSM8916 in the qcom driver.
Deleted features
- Drop support for the SiRF Marco that was never released to the
market.
- Drop SH7372 support as the support for this platform is removed
from the kernel"
* tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (40 commits)
sh-pfc: emev2 - Fix mangled author name
pinctrl: cherryview: Configure HiZ pins to be input when requested as GPIOs
pinctrl: imx25: fix numbering for pins
pinctrl: pinctrl-imx: don't use invalid value of conf_reg
pinctrl: qcom: delete pin_config_get/set pinconf operations
pinctrl: qcom: Add msm8916 pinctrl driver
DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding
pinctrl: qcom: increase variable size for register offsets
pinctrl: hide PCONFDUMP in #ifdef
pinctrl: rockchip: Only mask interrupts; never disable
pinctrl: zynq: Fix usb0 pins
pinctrl: sh-pfc: sh7372: Remove DT binding documentation
pinctrl: sh-pfc: sh7372: Remove PFC support
sh-pfc: Add emev2 pinmux support
sh-pfc: add macro to define pinmux without function
pinctrl: add driver for Amlogic Meson SoCs
staging: drivers: pinctrl: Fixed checkpatch.pl warnings
pinctrl: exynos: Add AUDIO pin controller for exynos7
sh-pfc: r8a7790: add MLB+ pin group
sh-pfc: r8a7791: add MLB+ pin group
...
54 files changed, 7863 insertions, 3158 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index 93ce12eb422a..fdd8046e650a 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -11,6 +11,7 @@ Required properties: "allwinner,sun5i-a10s-pinctrl" "allwinner,sun5i-a13-pinctrl" "allwinner,sun6i-a31-pinctrl" + "allwinner,sun6i-a31s-pinctrl" "allwinner,sun6i-a31-r-pinctrl" "allwinner,sun7i-a20-pinctrl" "allwinner,sun8i-a23-pinctrl" diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt new file mode 100644 index 000000000000..498caff6029e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt @@ -0,0 +1,186 @@ +Qualcomm MSM8916 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +MSM8916 platform. + +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,msm8916-pinctrl" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: <none> + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/interrupt-controller/irq.h> + +- gpio-controller: + Usage: required + Value type: <none> + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/gpio/gpio.h> + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: <string-array> + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio121, + sdc1_clk, + sdc1_cmd, + sdc1_data + sdc2_clk, + sdc2_cmd, + sdc2_data, + qdsd_cmd, + qdsd_data0, + qdsd_data1, + qdsd_data2, + qdsd_data3 + +- function: + Usage: required + Value type: <string> + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, atest_char0, + atest_char1, atest_char2, atest_char3, atest_combodac, atest_gpsadc0, + atest_gpsadc1, atest_tsens, atest_wlan0, atest_wlan1, backlight_en, + bimc_dte0,bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, + blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, + blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, + blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4, + blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2, + cam1_rst, cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, + display_5v, dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us, + ext_lpass, flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, + gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gpio, gsm0_tx0, gsm0_tx1, + gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, kpsns1, kpsns2, ldo_en, + ldo_update, mag_int, mdp_vsync, modem_tsync, m_voc, nav_pps, nav_tsync, + pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, pri_mi2s_ws, prng_rosc, + pwr_crypto_enabled_a, pwr_crypto_enabled_b, pwr_modem_enabled_a, + pwr_modem_enabled_b, pwr_nav_enabled_a, pwr_nav_enabled_b, + qdss_ctitrig_in_a0, qdss_ctitrig_in_a1, qdss_ctitrig_in_b0, + qdss_ctitrig_in_b1, qdss_ctitrig_out_a0, qdss_ctitrig_out_a1, + qdss_ctitrig_out_b0, qdss_ctitrig_out_b1, qdss_traceclk_a, + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, + qdss_tracedata_b, reset_n, sd_card, sd_write, sec_mi2s, smb_int, + ssbi_wtr0, ssbi_wtr1, uim1, uim2, uim3, uim_batt, wcss_bt, wcss_fm, + wcss_wlan, webcam1_rst + +- bias-disable: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as no pull. + +- bias-pull-down: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull down. + +- bias-pull-up: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull up. + +- output-high: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: <u32> + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8916-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart2: uart2-default { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + }; + + tx { + pins = "gpio4"; + drive-strength = <4>; + bias-disable; + }; + + rx { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index daef6fad6a5f..bfe72ec055e3 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -1,7 +1,7 @@ * Renesas Pin Function Controller (GPIO and Pin Mux/Config) -The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH7372, -SH73A0, R8A73A4 and R8A7740 it also acts as a GPIO controller. +The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0, +R8A73A4 and R8A7740 it also acts as a GPIO controller. Pin Control @@ -10,13 +10,13 @@ Pin Control Required Properties: - compatible: should be one of the following. + - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller. - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller. - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller. - - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller. - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. - reg: Base address and length of each memory resource used by the pin @@ -75,8 +75,7 @@ bias-disable, bias-pull-up and bias-pull-down. GPIO ---- -On SH7372, SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller -node. +On SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller node. Required Properties: diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 8425838a6dff..9d2a995293e6 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -171,6 +171,18 @@ Aliases: All the pin controller nodes should be represented in the aliases node using the following format 'pinctrl{n}' where n is a unique number for the alias. +Aliases for controllers compatible with "samsung,exynos7-pinctrl": +- pinctrl0: pin controller of ALIVE block, +- pinctrl1: pin controller of BUS0 block, +- pinctrl2: pin controller of NFC block, +- pinctrl3: pin controller of TOUCH block, +- pinctrl4: pin controller of FF block, +- pinctrl5: pin controller of ESE block, +- pinctrl6: pin controller of FSYS0 block, +- pinctrl7: pin controller of FSYS1 block, +- pinctrl8: pin controller of BUS1 block, +- pinctrl9: pin controller of AUDIO block, + Example: A pin-controller node with pin banks: pinctrl_0: pinctrl@11400000 { diff --git a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt index 6b33b9f18e88..f63fcb3ed352 100644 --- a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt +++ b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt @@ -16,17 +16,22 @@ mux function to select on those pin(s)/group(s), and various pin configuration parameters, such as input, output, pull up, pull down... The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. +and processed purely based on their content. The subnodes use the generic +pin multiplexing node layout from the standard pin control bindings +(see pinctrl-bindings.txt): -Required subnode-properties: -- ste,pins : An array of strings. Each string contains the name of a pin or - group. - -Optional subnode-properties: -- ste,function: A string containing the name of the function to mux to the +Required pin multiplexing subnode properties: +- function: A string containing the name of the function to mux to the pin or group. +- groups : An array of strings. Each string contains the name of a pin + group that will be combined with the function to form a multiplexing + set-up. -- ste,config: Handle of pin configuration node (e.g. ste,config = <&slpm_in_wkup_pdis>) +Required pin configuration subnode properties: +- pins: A string array describing the pins affected by the configuration + in the node. +- ste,config: Handle of pin configuration node + (e.g. ste,config = <&slpm_in_wkup_pdis>) - ste,input : <0/1/2> 0: input with no pull @@ -97,32 +102,32 @@ Example board file extract: uart0 { uart0_default_mux: uart0_mux { u0_default_mux { - ste,function = "u0"; - ste,pins = "u0_a_1"; + function = "u0"; + pins = "u0_a_1"; }; }; uart0_default_mode: uart0_default { uart0_default_cfg1 { - ste,pins = "GPIO0", "GPIO2"; + pins = "GPIO0", "GPIO2"; ste,input = <1>; }; uart0_default_cfg2 { - ste,pins = "GPIO1", "GPIO3"; + pins = "GPIO1", "GPIO3"; ste,output = <1>; }; }; uart0_sleep_mode: uart0_sleep { uart0_sleep_cfg1 { - ste,pins = "GPIO0", "GPIO2"; + pins = "GPIO0", "GPIO2"; ste,config = <&slpm_in_wkup_pdis>; }; uart0_sleep_cfg2 { - ste,pins = "GPIO1"; + pins = "GPIO1"; ste,config = <&slpm_out_hi_wkup_pdis>; }; uart0_sleep_cfg3 { - ste,pins = "GPIO3"; + pins = "GPIO3"; ste,config = <&slpm_out_wkup_pdis>; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt new file mode 100644 index 000000000000..b7b55a964f65 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt @@ -0,0 +1,104 @@ + Binding for Xilinx Zynq Pinctrl + +Required properties: +- compatible: "xlnx,zynq-pinctrl" +- syscon: phandle to SLCR +- reg: Offset and length of pinctrl space in SLCR + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Zynq's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, slew rate, etc. + +Each configuration node can consist of multiple nodes describing the pinmux and +pinconf options. Those nodes can be pinmux nodes or pinconf nodes. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Required properties for pinmux nodes are: + - groups: A list of pinmux groups. + - function: The name of a pinmux function to activate for the specified set + of groups. + +Required properties for configuration nodes: +One of: + - pins: a list of pin names + - groups: A list of pinmux groups. + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pinmux subnode: + groups, function + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pinconf subnode: + groups, pins, bias-disable, bias-high-impedance, bias-pull-up, slew-rate, + low-power-disable, low-power-enable + + Valid arguments for 'slew-rate' are '0' and '1' to select between slow and fast + respectively. + + Valid values for groups are: + ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp, + qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp, + spi0_1_grp - spi0_2_grp, spi1_0_grp - spi1_3_grp, sdio0_0_grp - sdio0_2_grp, + sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp, + sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand, + can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp, + uart1_0_grp - uart1_11_grp, i2c0_0_grp - i2c0_10_grp, i2c1_0_grp - i2c1_10_grp, + ttc0_0_grp - ttc0_2_grp, ttc1_0_grp - ttc1_2_grp, swdt0_0_grp - swdt0_4_grp, + gpio0_0_grp - gpio0_53_grp, usb0_0_grp, usb1_0_grp + + Valid values for pins are: + MIO0 - MIO53 + + Valid values for function are: + ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1, + spi0, spi1, sdio0, sdio0_pc, sdio0_cd, sdio0_wp, + sdio1, sdio1_pc, sdio1_cd, sdio1_wp, + smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1, + i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1 + +The following driver-specific properties as defined here are valid to specify in +a pin configuration subnode: + - io-standard: Configure the pin to use the selected IO standard according to + this mapping: + 1: LVCMOS18 + 2: LVCMOS25 + 3: LVCMOS33 + 4: HSTL + +Example: + pinctrl0: pinctrl@700 { + compatible = "xlnx,pinctrl-zynq"; + reg = <0x700 0x200>; + syscon = <&slcr>; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_10_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_10_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO49"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO48"; + bias-disable; + }; + }; + }; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index d014f22f387a..ee9f44ad7f02 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -96,6 +96,14 @@ config PINCTRL_FALCON depends on SOC_FALCON depends on PINCTRL_LANTIQ +config PINCTRL_MESON + bool + select PINMUX + select PINCONF + select GENERIC_PINCONF + select OF_GPIO + select REGMAP_MMIO + config PINCTRL_ROCKCHIP bool select PINMUX @@ -113,7 +121,7 @@ config PINCTRL_SINGLE This selects the device tree based generic pinctrl driver. config PINCTRL_SIRF - bool "CSR SiRFprimaII/SiRFmarco pin controller driver" + bool "CSR SiRFprimaII pin controller driver" depends on ARCH_SIRF select PINMUX select GPIOLIB_IRQCHIP @@ -191,6 +199,14 @@ config PINCTRL_PALMAS open drain configuration for the Palmas series devices like TPS65913, TPS80036 etc. +config PINCTRL_ZYNQ + bool "Pinctrl driver for Xilinx Zynq" + depends on ARCH_ZYNQ + select PINMUX + select GENERIC_PINCONF + help + This selectes the pinctrl driver for Xilinx Zynq. + source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/freescale/Kconfig" source "drivers/pinctrl/intel/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index c030b3db8034..0475206dd600 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -1,6 +1,6 @@ # generic pinmux support -ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG +subdir-ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG obj-$(CONFIG_PINCTRL) += core.o pinctrl-utils.o obj-$(CONFIG_PINMUX) += pinmux.o @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o +obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o @@ -35,6 +36,7 @@ obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o +obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-y += freescale/ diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 52f2b9404fe0..448f10986c28 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -437,7 +437,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; unsigned long config; - if (!pin_reg || !pin_reg->conf_reg) { + if (!pin_reg || pin_reg->conf_reg == -1) { seq_printf(s, "N/A"); return; } diff --git a/drivers/pinctrl/freescale/pinctrl-imx25.c b/drivers/pinctrl/freescale/pinctrl-imx25.c index 8d1013a040c9..faf635654312 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx25.c +++ b/drivers/pinctrl/freescale/pinctrl-imx25.c @@ -27,150 +27,148 @@ enum imx25_pads { MX25_PAD_RESERVE0 = 1, - MX25_PAD_RESERVE1 = 2, - MX25_PAD_A10 = 3, - MX25_PAD_A13 = 4, - MX25_PAD_A14 = 5, - MX25_PAD_A15 = 6, - MX25_PAD_A16 = 7, - MX25_PAD_A17 = 8, - MX25_PAD_A18 = 9, - MX25_PAD_A19 = 10, - MX25_PAD_A20 = 11, - MX25_PAD_A21 = 12, - MX25_PAD_A22 = 13, - MX25_PAD_A23 = 14, - MX25_PAD_A24 = 15, - MX25_PAD_A25 = 16, - MX25_PAD_EB0 = 17, - MX25_PAD_EB1 = 18, - MX25_PAD_OE = 19, - MX25_PAD_CS0 = 20, - MX25_PAD_CS1 = 21, - MX25_PAD_CS4 = 22, - MX25_PAD_CS5 = 23, - MX25_PAD_NF_CE0 = 24, - MX25_PAD_ECB = 25, - MX25_PAD_LBA = 26, - MX25_PAD_BCLK = 27, - MX25_PAD_RW = 28, - MX25_PAD_NFWE_B = 29, - MX25_PAD_NFRE_B = 30, - MX25_PAD_NFALE = 31, - MX25_PAD_NFCLE = 32, - MX25_PAD_NFWP_B = 33, - MX25_PAD_NFRB = 34, - MX25_PAD_D15 = 35, - MX25_PAD_D14 = 36, - MX25_PAD_D13 = 37, - MX25_PAD_D12 = 38, - MX25_PAD_D11 = 39, - MX25_PAD_D10 = 40, - MX25_PAD_D9 = 41, - MX25_PAD_D8 = 42, - MX25_PAD_D7 = 43, - MX25_PAD_D6 = 44, - MX25_PAD_D5 = 45, - MX25_PAD_D4 = 46, - MX25_PAD_D3 = 47, - MX25_PAD_D2 = 48, - MX25_PAD_D1 = 49, - MX25_PAD_D0 = 50, - MX25_PAD_LD0 = 51, - MX25_PAD_LD1 = 52, - MX25_PAD_LD2 = 53, - MX25_PAD_LD3 = 54, - MX25_PAD_LD4 = 55, - MX25_PAD_LD5 = 56, - MX25_PAD_LD6 = 57, - MX25_PAD_LD7 = 58, - MX25_PAD_LD8 = 59, - MX25_PAD_LD9 = 60, - MX25_PAD_LD10 = 61, - MX25_PAD_LD11 = 62, - MX25_PAD_LD12 = 63, - MX25_PAD_LD13 = 64, - MX25_PAD_LD14 = 65, - MX25_PAD_LD15 = 66, - MX25_PAD_HSYNC = 67, - MX25_PAD_VSYNC = 68, - MX25_PAD_LSCLK = 69, - MX25_PAD_OE_ACD = 70, - MX25_PAD_CONTRAST = 71, - MX25_PAD_PWM = 72, - MX25_PAD_CSI_D2 = 73, - MX25_PAD_CSI_D3 = 74, - MX25_PAD_CSI_D4 = 75, - MX25_PAD_CSI_D5 = 76, - MX25_PAD_CSI_D6 = 77, - MX25_PAD_CSI_D7 = 78, - MX25_PAD_CSI_D8 = 79, - MX25_PAD_CSI_D9 = 80, - MX25_PAD_CSI_MCLK = 81, - MX25_PAD_CSI_VSYNC = 82, - MX25_PAD_CSI_HSYNC = 83, - MX25_PAD_CSI_PIXCLK = 84, - MX25_PAD_I2C1_CLK = 85, - MX25_PAD_I2C1_DAT = 86, - MX25_PAD_CSPI1_MOSI = 87, - MX25_PAD_CSPI1_MISO = 88, - MX25_PAD_CSPI1_SS0 = 89, - MX25_PAD_CSPI1_SS1 = 90, - MX25_PAD_CSPI1_SCLK = 91, - MX25_PAD_CSPI1_RDY = 92, - MX25_PAD_UART1_RXD = 93, - MX25_PAD_UART1_TXD = 94, - MX25_PAD_UART1_RTS = 95, - MX25_PAD_UART1_CTS = 96, - MX25_PAD_UART2_RXD = 97, - MX25_PAD_UART2_TXD = 98, - MX25_PAD_UART2_RTS = 99, - MX25_PAD_UART2_CTS = 100, - MX25_PAD_SD1_CMD = 101, - MX25_PAD_SD1_CLK = 102, - MX25_PAD_SD1_DATA0 = 103, - MX25_PAD_SD1_DATA1 = 104, - MX25_PAD_SD1_DATA2 = 105, - MX25_PAD_SD1_DATA3 = 106, - MX25_PAD_KPP_ROW0 = 107, - MX25_PAD_KPP_ROW1 = 108, - MX25_PAD_KPP_ROW2 = 109, - MX25_PAD_KPP_ROW3 = 110, - MX25_PAD_KPP_COL0 = 111, - MX25_PAD_KPP_COL1 = 112, - MX25_PAD_KPP_COL2 = 113, - MX25_PAD_KPP_COL3 = 114, - MX25_PAD_FEC_MDC = 115, - MX25_PAD_FEC_MDIO = 116, - MX25_PAD_FEC_TDATA0 = 117, - MX25_PAD_FEC_TDATA1 = 118, - MX25_PAD_FEC_TX_EN = 119, - MX25_PAD_FEC_RDATA0 = 120, - MX25_PAD_FEC_RDATA1 = 121, - MX25_PAD_FEC_RX_DV = 122, - MX25_PAD_FEC_TX_CLK = 123, - MX25_PAD_RTCK = 124, - MX25_PAD_DE_B = 125, - MX25_PAD_GPIO_A = 126, - MX25_PAD_GPIO_B = 127, - MX25_PAD_GPIO_C = 128, - MX25_PAD_GPIO_D = 129, - MX25_PAD_GPIO_E = 130, - MX25_PAD_GPIO_F = 131, - MX25_PAD_EXT_ARMCLK = 132, - MX25_PAD_UPLL_BYPCLK = 133, - MX25_PAD_VSTBY_REQ = 134, - MX25_PAD_VSTBY_ACK = 135, - MX25_PAD_POWER_FAIL = 136, - MX25_PAD_CLKO = 137, - MX25_PAD_BOOT_MODE0 = 138, - MX25_PAD_BOOT_MODE1 = 139, + MX25_PAD_A10 = 2, + MX25_PAD_A13 = 3, + MX25_PAD_A14 = 4, + MX25_PAD_A15 = 5, + MX25_PAD_A16 = 6, + MX25_PAD_A17 = 7, + MX25_PAD_A18 = 8, + MX25_PAD_A19 = 9, + MX25_PAD_A20 = 10, + MX25_PAD_A21 = 11, + MX25_PAD_A22 = 12, + MX25_PAD_A23 = 13, + MX25_PAD_A24 = 14, + MX25_PAD_A25 = 15, + MX25_PAD_EB0 = 16, + MX25_PAD_EB1 = 17, + MX25_PAD_OE = 18, + MX25_PAD_CS0 = 19, + MX25_PAD_CS1 = 20, + MX25_PAD_CS4 = 21, + MX25_PAD_CS5 = 22, + MX25_PAD_NF_CE0 = 23, + MX25_PAD_ECB = 24, + MX25_PAD_LBA = 25, + MX25_PAD_BCLK = 26, + MX25_PAD_RW = 27, + MX25_PAD_NFWE_B = 28, + MX25_PAD_NFRE_B = 29, + MX25_PAD_NFALE = 30, + MX25_PAD_NFCLE = 31, + MX25_PAD_NFWP_B = 32, + MX25_PAD_NFRB = 33, + MX25_PAD_D15 = 34, + MX25_PAD_D14 = 35, + MX25_PAD_D13 = 36, + MX25_PAD_D12 = 37, + MX25_PAD_D11 = 38, + MX25_PAD_D10 = 39, + MX25_PAD_D9 = 40, + MX25_PAD_D8 = 41, + MX25_PAD_D7 = 42, + MX25_PAD_D6 = 43, + MX25_PAD_D5 = 44, + MX25_PAD_D4 = 45, + MX25_PAD_D3 = 46, + MX25_PAD_D2 = 47, + MX25_PAD_D1 = 48, + MX25_PAD_D0 = 49, + MX25_PAD_LD0 = 50, + MX25_PAD_LD1 = 51, + MX25_PAD_LD2 = 52, + MX25_PAD_LD3 = 53, + MX25_PAD_LD4 = 54, + MX25_PAD_LD5 = 55, + MX25_PAD_LD6 = 56, + MX25_PAD_LD7 = 57, + MX25_PAD_LD8 = 58, + MX25_PAD_LD9 = 59, + MX25_PAD_LD10 = 60, + MX25_PAD_LD11 = 61, + MX25_PAD_LD12 = 62, + MX25_PAD_LD13 = 63, + MX25_PAD_LD14 = 64, + MX25_PAD_LD15 = 65, + MX25_PAD_HSYNC = 66, + MX25_PAD_VSYNC = 67, + MX25_PAD_LSCLK = 68, + MX25_PAD_OE_ACD = 69, + MX25_PAD_CONTRAST = 70, + MX25_PAD_PWM = 71, + MX25_PAD_CSI_D2 = 72, + MX25_PAD_CSI_D3 = 73, + MX25_PAD_CSI_D4 = 74, + MX25_PAD_CSI_D5 = 75, + MX25_PAD_CSI_D6 = 76, + MX25_PAD_CSI_D7 = 77, + MX25_PAD_CSI_D8 = 78, + MX25_PAD_CSI_D9 = 79, + MX25_PAD_CSI_MCLK = 80, + MX25_PAD_CSI_VSYNC = 81, + MX25_PAD_CSI_HSYNC = 82, + MX25_PAD_CSI_PIXCLK = 83, + MX25_PAD_I2C1_CLK = 84, + MX25_PAD_I2C1_DAT = 85, + MX25_PAD_CSPI1_MOSI = 86, + MX25_PAD_CSPI1_MISO = 87, + MX25_PAD_CSPI1_SS0 = 88, + MX25_PAD_CSPI1_SS1 = 89, + MX25_PAD_CSPI1_SCLK = 90, + MX25_PAD_CSPI1_RDY = 91, + MX25_PAD_UART1_RXD = 92, + MX25_PAD_UART1_TXD = 93, + MX25_PAD_UART1_RTS = 94, + MX25_PAD_UART1_CTS = 95, + MX25_PAD_UART2_RXD = 96, + MX25_PAD_UART2_TXD = 97, + MX25_PAD_UART2_RTS = 98, + MX25_PAD_UART2_CTS = 99, + MX25_PAD_SD1_CMD = 100, + MX25_PAD_SD1_CLK = 101, + MX25_PAD_SD1_DATA0 = 102, + MX25_PAD_SD1_DATA1 = 103, + MX25_PAD_SD1_DATA2 = 104, + MX25_PAD_SD1_DATA3 = 105, + MX25_PAD_KPP_ROW0 = 106, + MX25_PAD_KPP_ROW1 = 107, + MX25_PAD_KPP_ROW2 = 108, + MX25_PAD_KPP_ROW3 = 109, + MX25_PAD_KPP_COL0 = 110, + MX25_PAD_KPP_COL1 = 111, + MX25_PAD_KPP_COL2 = 112, + MX25_PAD_KPP_COL3 = 113, + MX25_PAD_FEC_MDC = 114, + MX25_PAD_FEC_MDIO = 115, + MX25_PAD_FEC_TDATA0 = 116, + MX25_PAD_FEC_TDATA1 = 117, + MX25_PAD_FEC_TX_EN = 118, + MX25_PAD_FEC_RDATA0 = 119, + MX25_PAD_FEC_RDATA1 = 120, + MX25_PAD_FEC_RX_DV = 121, + MX25_PAD_FEC_TX_CLK = 122, + MX25_PAD_RTCK = 123, + MX25_PAD_DE_B = 124, + MX25_PAD_GPIO_A = 125, + MX25_PAD_GPIO_B = 126, + MX25_PAD_GPIO_C = 127, + MX25_PAD_GPIO_D = 128, + MX25_PAD_GPIO_E = 129, + MX25_PAD_GPIO_F = 130, + MX25_PAD_EXT_ARMCLK = 131, + MX25_PAD_UPLL_BYPCLK = 132, + MX25_PAD_VSTBY_REQ = 133, + MX25_PAD_VSTBY_ACK = 134, + MX25_PAD_POWER_FAIL = 135, + MX25_PAD_CLKO = 136, + MX25_PAD_BOOT_MODE0 = 137, + MX25_PAD_BOOT_MODE1 = 138, }; /* Pad names for the pinmux subsystem */ static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX25_PAD_RESERVE0), - IMX_PINCTRL_PIN(MX25_PAD_RESERVE1), IMX_PINCTRL_PIN(MX25_PAD_A10), IMX_PINCTRL_PIN(MX25_PAD_A13), IMX_PINCTRL_PIN(MX25_PAD_A14), diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index e9f8b39d1a9f..3034fd03bced 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -148,6 +148,11 @@ struct chv_community { size_t ngpios; }; +struct chv_pin_context { + u32 padctrl0; + u32 padctrl1; +}; + /** * struct chv_pinctrl - CHV pinctrl private structure * @dev: Pointer to the parent device @@ -172,6 +177,8 @@ struct chv_pinctrl { spinlock_t lock; unsigned intr_lines[16]; const struct chv_community *community; + u32 saved_intmask; + struct chv_pin_context *saved_pin_context; }; #define gpiochip_to_pinctrl(c) container_of(c, struct chv_pinctrl, chip) @@ -873,9 +880,22 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, value &= ~CHV_PADCTRL1_INVRXTX_MASK; chv_writel(value, reg); - /* Switch to a GPIO mode */ reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); - value = readl(reg) | CHV_PADCTRL0_GPIOEN; + value = readl(reg); + + /* + * If the pin is in HiZ mode (both TX and RX buffers are + * disabled) we turn it to be input now. + */ + if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == + (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { + value &= ~CHV_PADCTRL0_GPIOCFG_MASK; + value |= CHV_PADCTRL0_GPIOCFG_GPI << + CHV_PADCTRL0_GPIOCFG_SHIFT; + } + + /* Switch to a GPIO mode */ + value |= CHV_PADCTRL0_GPIOEN; chv_writel(value, reg); } @@ -1443,6 +1463,14 @@ static int chv_pinctrl_probe(struct platform_device *pdev) spin_lock_init(&pctrl->lock); pctrl->dev = &pdev->dev; +#ifdef CONFIG_PM_SLEEP + pctrl->saved_pin_context = devm_kcalloc(pctrl->dev, + pctrl->community->npins, sizeof(*pctrl->saved_pin_context), + GFP_KERNEL); + if (!pctrl->saved_pin_context) + return -ENOMEM; +#endif + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pctrl->regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(pctrl->regs)) @@ -1486,6 +1514,94 @@ static int chv_pinctrl_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM_SLEEP +static int chv_pinctrl_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); + int i; + + pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); + + for (i = 0; i < pctrl->community->npins; i++) { + const struct pinctrl_pin_desc *desc; + struct chv_pin_context *ctx; + void __iomem *reg; + + desc = &pctrl->community->pins[i]; + if (chv_pad_locked(pctrl, desc->number)) + continue; + + ctx = &pctrl->saved_pin_context[i]; + + reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); + ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; + + reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); + ctx->padctrl1 = readl(reg); + } + + return 0; +} + +static int chv_pinctrl_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); + int i; + + /* + * Mask all interrupts before restoring per-pin configuration + * registers because we don't know in which state BIOS left them + * upon exiting suspend. + */ + chv_writel(0, pctrl->regs + CHV_INTMASK); + + for (i = 0; i < pctrl->community->npins; i++) { + const struct pinctrl_pin_desc *desc; + const struct chv_pin_context *ctx; + void __iomem *reg; + u32 val; + + desc = &pctrl->community->pins[i]; + if (chv_pad_locked(pctrl, desc->number)) + continue; + + ctx = &pctrl->saved_pin_context[i]; + + /* Only restore if our saved state differs from the current */ + reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); + val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; + if (ctx->padctrl0 != val) { + chv_writel(ctx->padctrl0, reg); + dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", + desc->number, readl(reg)); + } + + reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); + val = readl(reg); + if (ctx->padctrl1 != val) { + chv_writel(ctx->padctrl1, reg); + dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", + desc->number, readl(reg)); + } + } + + /* + * Now that all pins are restored to known state, we can restore + * the interrupt mask register as well. + */ + chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); + chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); + + return 0; +} +#endif + +static const struct dev_pm_ops chv_pinctrl_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend, chv_pinctrl_resume) +}; + static const struct acpi_device_id chv_pinctrl_acpi_match[] = { { "INT33FF" }, { } @@ -1497,7 +1613,7 @@ static struct platform_driver chv_pinctrl_driver = { .remove = chv_pinctrl_remove, .driver = { .name = "cherryview-pinctrl", - .owner = THIS_MODULE, + .pm = &chv_pinctrl_pm_ops, .acpi_match_table = chv_pinctrl_acpi_match, }, }; diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile new file mode 100644 index 000000000000..eafc216067a4 --- /dev/null +++ b/drivers/pinctrl/meson/Makefile @@ -0,0 +1,2 @@ +obj-y += pinctrl-meson8.o +obj-y += pinctrl-meson.o diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c new file mode 100644 index 000000000000..a2bf49ce16e7 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -0,0 +1,761 @@ +/* + * Pin controller and GPIO driver for Amlogic Meson SoCs + * + * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, + * BOOT,CARD for meson6 and X,Y,DV,H,Z,AO,BOOT,CARD for meson8) and + * each bank has a variable number of pins. + * + * The AO bank is special because it belongs to the Always-On power + * domain which can't be powered off; the bank also uses a set of + * registers different from the other banks. + * + * For each of the two power domains (regular and always-on) there are + * 4 different register ranges that control the following properties + * of the pins: + * 1) pin muxing + * 2) pull enable/disable + * 3) pull up/down + * 4) GPIO direction, output value, input value + * + * In some cases the register ranges for pull enable and pull + * direction are the same and thus there are only 3 register ranges. + * + * Every pinmux group can be enabled by a specific bit in the first + * register range of the domain; when all groups for a given pin are + * disabled the pin acts as a GPIO. + * + * For the pull and GPIO configuration every bank uses a contiguous + * set of bits in the register sets described above; the same register + * can be shared by more banks with different offsets. + * + * In addition to this there are some registers shared between all + * banks that control the IRQ functionality. This feature is not + * supported at the moment by the driver. + */ + +#include <linux/device.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "pinctrl-meson.h" + +/** + * meson_get_bank() - find the bank containing a given pin + * + * @domain: the domain containing the pin + * @pin: the pin number + * @bank: the found bank + * + * Return: 0 on success, a negative value on error + */ +static int meson_get_bank(struct meson_domain *domain, unsigned int pin, + struct meson_bank **bank) +{ + int i; + + for (i = 0; i < domain->data->num_banks; i++) { + if (pin >= domain->data->banks[i].first && + pin <= domain->data->banks[i].last) { + *bank = &domain->data->banks[i]; + return 0; + } + } + + return -EINVAL; +} + +/** + * meson_get_domain_and_bank() - find domain and bank containing a given pin + * + * @pc: Meson pin controller device + * @pin: the pin number + * @domain: the found domain + * @bank: the found bank + * + * Return: 0 on success, a negative value on error + */ +static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin, + struct meson_domain **domain, + struct meson_bank **bank) +{ + struct meson_domain *d; + int i; + + for (i = 0; i < pc->data->num_domains; i++) { + d = &pc->domains[i]; + if (pin >= d->data->pin_base && + pin < d->data->pin_base + d->data->num_pins) { + *domain = d; + return meson_get_bank(d, pin, bank); + } + } + + return -EINVAL; +} + +/** + * meson_calc_reg_and_bit() - calculate register and bit for a pin + * + * @bank: the bank containing the pin + * @pin: the pin number + * @reg_type: the type of register needed (pull-enable, pull, etc...) + * @reg: the computed register offset + * @bit: the computed bit + */ +static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, + enum meson_reg_type reg_type, + unsigned int *reg, unsigned int *bit) +{ + struct meson_reg_desc *desc = &bank->regs[reg_type]; + + *reg = desc->reg * 4; + *bit = desc->bit + pin - bank->first; +} + +static int meson_get_groups_count(struct pinctrl_dev *pcdev) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + + return pc->data->num_groups; +} + +static const char *meson_get_group_name(struct pinctrl_dev *pcdev, + unsigned selector) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + + return pc->data->groups[selector].name; +} + +static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, + const unsigned **pins, unsigned *num_pins) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + + *pins = pc->data->groups[selector].pins; + *num_pins = pc->data->groups[selector].num_pins; + + return 0; +} + +static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " %s", dev_name(pcdev->dev)); +} + +static const struct pinctrl_ops meson_pctrl_ops = { + .get_groups_count = meson_get_groups_count, + .get_group_name = meson_get_group_name, + .get_group_pins = meson_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_dt_free_map, + .pin_dbg_show = meson_pin_dbg_show, +}; + +/** + * meson_pmx_disable_other_groups() - disable other groups using a given pin + * + * @pc: meson pin controller device + * @pin: number of the pin + * @sel_group: index of the selected group, or -1 if none + * + * The function disables all pinmux groups using a pin except the + * selected one. If @sel_group is -1 all groups are disabled, leaving + * the pin in GPIO mode. + */ +static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc, + unsigned int pin, int sel_group) +{ + struct meson_pmx_group *group; + struct meson_domain *domain; + int i, j; + + for (i = 0; i < pc->data->num_groups; i++) { + group = &pc->data->groups[i]; + if (group->is_gpio || i == sel_group) + continue; + + for (j = 0; j < group->num_pins; j++) { + if (group->pins[j] == pin) { + /* We have found a group using the pin */ + domain = &pc->domains[group->domain]; + regmap_update_bits(domain->reg_mux, + group->reg * 4, + BIT(group->bit), 0); + } + } + } +} + +static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num, + unsigned group_num) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + struct meson_pmx_func *func = &pc->data->funcs[func_num]; + struct meson_pmx_group *group = &pc->data->groups[group_num]; + struct meson_domain *domain = &pc->domains[group->domain]; + int i, ret = 0; + + dev_dbg(pc->dev, "enable function %s, group %s\n", func->name, + group->name); + + /* + * Disable groups using the same pin. + * The selected group is not disabled to avoid glitches. + */ + for (i = 0; i < group->num_pins; i++) + meson_pmx_disable_other_groups(pc, group->pins[i], group_num); + + /* Function 0 (GPIO) doesn't need any additional setting */ + if (func_num) + ret = regmap_update_bits(domain->reg_mux, group->reg * 4, + BIT(group->bit), BIT(group->bit)); + + return ret; +} + +static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + + meson_pmx_disable_other_groups(pc, range->pin_base + offset, -1); + + return 0; +} + +static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + + return pc->data->num_funcs; +} + +static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, + unsigned selector) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + + return pc->data->funcs[selector].name; +} + +static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + + *groups = pc->data->funcs[selector].groups; + *num_groups = pc->data->funcs[selector].num_groups; + + return 0; +} + +static const struct pinmux_ops meson_pmx_ops = { + .set_mux = meson_pmx_set_mux, + .get_functions_count = meson_pmx_get_funcs_count, + .get_function_name = meson_pmx_get_func_name, + .get_function_groups = meson_pmx_get_groups, + .gpio_request_enable = meson_pmx_request_gpio, +}; + +static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, + unsigned long *configs, unsigned num_configs) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + struct meson_domain *domain; + struct meson_bank *bank; + enum pin_config_param param; + unsigned int reg, bit; + int i, ret; + u16 arg; + + ret = meson_get_domain_and_bank(pc, pin, &domain, &bank); + if (ret) + return ret; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + dev_dbg(pc->dev, "pin %u: disable bias\n", pin); + + meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); + ret = regmap_update_bits(domain->reg_pull, reg, + BIT(bit), 0); + if (ret) + return ret; + break; + case PIN_CONFIG_BIAS_PULL_UP: + dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin); + + meson_calc_reg_and_bit(bank, pin, REG_PULLEN, + ®, &bit); + ret = regmap_update_bits(domain->reg_pullen, reg, + BIT(bit), BIT(bit)); + if (ret) + return ret; + + meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); + ret = regmap_update_bits(domain->reg_pull, reg, + BIT(bit), BIT(bit)); + if (ret) + return ret; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin); + + meson_calc_reg_and_bit(bank, pin, REG_PULLEN, + ®, &bit); + ret = regmap_update_bits(domain->reg_pullen, reg, + BIT(bit), BIT(bit)); + if (ret) + return ret; + + meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); + ret = regmap_update_bits(domain->reg_pull, reg, + BIT(bit), 0); + if (ret) + return ret; + break; + default: + return -ENOTSUPP; + } + } + + return 0; +} + +static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) +{ + struct meson_domain *domain; + struct meson_bank *bank; + unsigned int reg, bit, val; + int ret, conf; + + ret = meson_get_domain_and_bank(pc, pin, &domain, &bank); + if (ret) + return ret; + + meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); + + ret = regmap_read(domain->reg_pullen, reg, &val); + if (ret) + return ret; + + if (!(val & BIT(bit))) { + conf = PIN_CONFIG_BIAS_DISABLE; + } else { + meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); + + ret = regmap_read(domain->reg_pull, reg, &val); + if (ret) + return ret; + + if (val & BIT(bit)) + conf = PIN_CONFIG_BIAS_PULL_UP; + else + conf = PIN_CONFIG_BIAS_PULL_DOWN; + } + + return conf; +} + +static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, + unsigned long *config) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + enum pin_config_param param = pinconf_to_config_param(*config); + u16 arg; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + if (meson_pinconf_get_pull(pc, pin) == param) + arg = 1; + else + return -EINVAL; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); + + return 0; +} + +static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, + unsigned int num_group, + unsigned long *configs, unsigned num_configs) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + struct meson_pmx_group *group = &pc->data->groups[num_group]; + int i; + + dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); + + for (i = 0; i < group->num_pins; i++) { + meson_pinconf_set(pcdev, group->pins[i], configs, + num_configs); + } + + return 0; +} + +static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, + unsigned int group, unsigned long *config) +{ + return -ENOSYS; +} + +static const struct pinconf_ops meson_pinconf_ops = { + .pin_config_get = meson_pinconf_get, + .pin_config_set = meson_pinconf_set, + .pin_config_group_get = meson_pinconf_group_get, + .pin_config_group_set = meson_pinconf_group_set, + .is_generic = true, +}; + +static inline struct meson_domain *to_meson_domain(struct gpio_chip *chip) +{ + return container_of(chip, struct meson_domain, chip); +} + +static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio) +{ + return pinctrl_request_gpio(chip->base + gpio); +} + +static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio) +{ + struct meson_domain *domain = to_meson_domain(chip); + + pinctrl_free_gpio(domain->data->pin_base + gpio); +} + +static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) +{ + struct meson_domain *domain = to_meson_domain(chip); + unsigned int reg, bit, pin; + struct meson_bank *bank; + int ret; + + pin = domain->data->pin_base + gpio; + ret = meson_get_bank(domain, pin, &bank); + if (ret) + return ret; + + meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); + + return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), BIT(bit)); +} + +static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, + int value) +{ + struct meson_domain *domain = to_meson_domain(chip); + unsigned int reg, bit, pin; + struct meson_bank *bank; + int ret; + + pin = domain->data->pin_base + gpio; + ret = meson_get_bank(domain, pin, &bank); + if (ret) + return ret; + + meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); + ret = regmap_update_bits(domain->reg_gpio, reg, BIT(bit), 0); + if (ret) + return ret; + + meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); + return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), + value ? BIT(bit) : 0); +} + +static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) +{ + struct meson_domain *domain = to_meson_domain(chip); + unsigned int reg, bit, pin; + struct meson_bank *bank; + int ret; + + pin = domain->data->pin_base + gpio; + ret = meson_get_bank(domain, pin, &bank); + if (ret) + return; + + meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); + regmap_update_bits(domain->reg_gpio, reg, BIT(bit), + value ? BIT(bit) : 0); +} + +static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) +{ + struct meson_domain *domain = to_meson_domain(chip); + unsigned int reg, bit, val, pin; + struct meson_bank *bank; + int ret; + + pin = domain->data->pin_base + gpio; + ret = meson_get_bank(domain, pin, &bank); + if (ret) + return ret; + + meson_calc_reg_and_bit(bank, pin, REG_IN, ®, &bit); + regmap_read(domain->reg_gpio, reg, &val); + + return !!(val & BIT(bit)); +} + +static const struct of_device_id meson_pinctrl_dt_match[] = { + { + .compatible = "amlogic,meson8-pinctrl", + .data = &meson8_pinctrl_data, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match); + +static int meson_gpiolib_register(struct meson_pinctrl *pc) +{ + struct meson_domain *domain; + int i, ret; + + for (i = 0; i < pc->data->num_domains; i++) { + domain = &pc->domains[i]; + + domain->chip.label = domain->data->name; + domain->chip.dev = pc->dev; + domain->chip.request = meson_gpio_request; + domain->chip.free = meson_gpio_free; + domain->chip.direction_input = meson_gpio_direction_input; + domain->chip.direction_output = meson_gpio_direction_output; + domain->chip.get = meson_gpio_get; + domain->chip.set = meson_gpio_set; + domain->chip.base = -1; + domain->chip.ngpio = domain->data->num_pins; + domain->chip.can_sleep = false; + domain->chip.of_node = domain->of_node; + domain->chip.of_gpio_n_cells = 2; + + ret = gpiochip_add(&domain->chip); + if (ret) { + dev_err(pc->dev, "can't add gpio chip %s\n", + domain->data->name); + goto fail; + } + + ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev), + 0, domain->data->pin_base, + domain->chip.ngpio); + if (ret) { + dev_err(pc->dev, "can't add pin range\n"); + goto fail; + } + } + + return 0; +fail: + for (i--; i >= 0; i--) + gpiochip_remove(&pc->domains[i].chip); + + return ret; +} + +static struct meson_domain_data *meson_get_domain_data(struct meson_pinctrl *pc, + struct device_node *np) +{ + int i; + + for (i = 0; i < pc->data->num_domains; i++) { + if (!strcmp(np->name, pc->data->domain_data[i].name)) + return &pc->data->domain_data[i]; + } + + return NULL; +} + +static struct regmap_config meson_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static struct regmap *meson_map_resource(struct meson_pinctrl *pc, + struct device_node *node, char *name) +{ + struct resource res; + void __iomem *base; + int i; + + i = of_property_match_string(node, "reg-names", name); + if (of_address_to_resource(node, i, &res)) + return ERR_PTR(-ENOENT); + + base = devm_ioremap_resource(pc->dev, &res); + if (IS_ERR(base)) + return ERR_CAST(base); + + meson_regmap_config.max_register = resource_size(&res) - 4; + meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, + "%s-%s", node->name, + name); + if (!meson_regmap_config.name) + return ERR_PTR(-ENOMEM); + + return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); +} + +static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, + struct device_node *node) +{ + struct device_node *np; + struct meson_domain *domain; + int i = 0, num_domains = 0; + + for_each_child_of_node(node, np) { + if (!of_find_property(np, "gpio-controller", NULL)) + continue; + num_domains++; + } + + if (num_domains != pc->data->num_domains) { + dev_err(pc->dev, "wrong number of subnodes\n"); + return -EINVAL; + } + + pc->domains = devm_kzalloc(pc->dev, num_domains * + sizeof(struct meson_domain), GFP_KERNEL); + if (!pc->domains) + return -ENOMEM; + + for_each_child_of_node(node, np) { + if (!of_find_property(np, "gpio-controller", NULL)) + continue; + + domain = &pc->domains[i]; + + domain->data = meson_get_domain_data(pc, np); + if (!domain->data) { + dev_err(pc->dev, "domain data not found for node %s\n", + np->name); + return -ENODEV; + } + + domain->of_node = np; + + domain->reg_mux = meson_map_resource(pc, np, "mux"); + if (IS_ERR(domain->reg_mux)) { + dev_err(pc->dev, "mux registers not found\n"); + return PTR_ERR(domain->reg_mux); + } + + domain->reg_pull = meson_map_resource(pc, np, "pull"); + if (IS_ERR(domain->reg_pull)) { + dev_err(pc->dev, "pull registers not found\n"); + return PTR_ERR(domain->reg_pull); + } + + domain->reg_pullen = meson_map_resource(pc, np, "pull-enable"); + /* Use pull region if pull-enable one is not present */ + if (IS_ERR(domain->reg_pullen)) + domain->reg_pullen = domain->reg_pull; + + domain->reg_gpio = meson_map_resource(pc, np, "gpio"); + if (IS_ERR(domain->reg_gpio)) { + dev_err(pc->dev, "gpio registers not found\n"); + return PTR_ERR(domain->reg_gpio); + } + + i++; + } + + return 0; +} + +static int meson_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + struct device *dev = &pdev->dev; + struct meson_pinctrl *pc; + int ret; + + pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); + if (!pc) + return -ENOMEM; + + pc->dev = dev; + match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node); + pc->data = (struct meson_pinctrl_data *)match->data; + + ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node); + if (ret) + return ret; + + pc->desc.name = "pinctrl-meson"; + pc->desc.owner = THIS_MODULE; + pc->desc.pctlops = &meson_pctrl_ops; + pc->desc.pmxops = &meson_pmx_ops; + pc->desc.confops = &meson_pinconf_ops; + pc->desc.pins = pc->data->pins; + pc->desc.npins = pc->data->num_pins; + + pc->pcdev = pinctrl_register(&pc->desc, pc->dev, pc); + if (!pc->pcdev) { + dev_err(pc->dev, "can't register pinctrl device"); + return -EINVAL; + } + + ret = meson_gpiolib_register(pc); + if (ret) { + pinctrl_unregister(pc->pcdev); + return ret; + } + + return 0; +} + +static struct platform_driver meson_pinctrl_driver = { + .probe = meson_pinctrl_probe, + .driver = { + .name = "meson-pinctrl", + .of_match_table = meson_pinctrl_dt_match, + }, +}; +module_platform_driver(meson_pinctrl_driver); + +MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); +MODULE_DESCRIPTION("Amlogic Meson pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h new file mode 100644 index 000000000000..bfea8adc7953 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -0,0 +1,209 @@ +/* + * Pin controller and GPIO driver for Amlogic Meson SoCs + * + * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/gpio.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/regmap.h> +#include <linux/types.h> + +/** + * struct meson_pmx_group - a pinmux group + * + * @name: group name + * @pins: pins in the group + * @num_pins: number of pins in the group + * @is_gpio: whether the group is a single GPIO group + * @reg: register offset for the group in the domain mux registers + * @bit bit index enabling the group + * @domain: index of the domain this group belongs to + */ +struct meson_pmx_group { + const char *name; + const unsigned int *pins; + unsigned int num_pins; + bool is_gpio; + unsigned int reg; + unsigned int bit; + unsigned int domain; +}; + +/** + * struct meson_pmx_func - a pinmux function + * + * @name: function name + * @groups: groups in the function + * @num_groups: number of groups in the function + */ +struct meson_pmx_func { + const char *name; + const char * const *groups; + unsigned int num_groups; +}; + +/** + * struct meson_reg_desc - a register descriptor + * + * @reg: register offset in the regmap + * @bit: bit index in register + * + * The structure describes the information needed to control pull, + * pull-enable, direction, etc. for a single pin + */ +struct meson_reg_desc { + unsigned int reg; + unsigned int bit; +}; + +/** + * enum meson_reg_type - type of registers encoded in @meson_reg_desc + */ +enum meson_reg_type { + REG_PULLEN, + REG_PULL, + REG_DIR, + REG_OUT, + REG_IN, + NUM_REG, +}; + +/** + * struct meson bank + * + * @name: bank name + * @first: first pin of the bank + * @last: last pin of the bank + * @regs: array of register descriptors + * + * A bank represents a set of pins controlled by a contiguous set of + * bits in the domain registers. The structure specifies which bits in + * the regmap control the different functionalities. Each member of + * the @regs array refers to the first pin of the bank. + */ +struct meson_bank { + const char *name; + unsigned int first; + unsigned int last; + struct meson_reg_desc regs[NUM_REG]; +}; + +/** + * struct meson_domain_data - domain platform data + * + * @name: name of the domain + * @banks: set of banks belonging to the domain + * @num_banks: number of banks in the domain + */ +struct meson_domain_data { + const char *name; + struct meson_bank *banks; + unsigned int num_banks; + unsigned int pin_base; + unsigned int num_pins; +}; + +/** + * struct meson_domain + * + * @reg_mux: registers for mux settings + * @reg_pullen: registers for pull-enable settings + * @reg_pull: registers for pull settings + * @reg_gpio: registers for gpio settings + * @chip: gpio chip associated with the domain + * @data; platform data for the domain + * @node: device tree node for the domain + * + * A domain represents a set of banks controlled by the same set of + * registers. + */ +struct meson_domain { + struct regmap *reg_mux; + struct regmap *reg_pullen; + struct regmap *reg_pull; + struct regmap *reg_gpio; + + struct gpio_chip chip; + struct meson_domain_data *data; + struct device_node *of_node; +}; + +struct meson_pinctrl_data { + const struct pinctrl_pin_desc *pins; + struct meson_pmx_group *groups; + struct meson_pmx_func *funcs; + struct meson_domain_data *domain_data; + unsigned int num_pins; + unsigned int num_groups; + unsigned int num_funcs; + unsigned int num_domains; +}; + +struct meson_pinctrl { + struct device *dev; + struct pinctrl_dev *pcdev; + struct pinctrl_desc desc; + struct meson_pinctrl_data *data; + struct meson_domain *domains; +}; + +#define GROUP(grp, r, b) \ + { \ + .name = #grp, \ + .pins = grp ## _pins, \ + .num_pins = ARRAY_SIZE(grp ## _pins), \ + .reg = r, \ + .bit = b, \ + .domain = 0, \ + } + +#define GPIO_GROUP(gpio) \ + { \ + .name = #gpio, \ + .pins = (const unsigned int[]){ PIN_ ## gpio}, \ + .num_pins = 1, \ + .is_gpio = true, \ + } + +#define GROUP_AO(grp, r, b) \ + { \ + .name = #grp, \ + .pins = grp ## _pins, \ + .num_pins = ARRAY_SIZE(grp ## _pins), \ + .reg = r, \ + .bit = b, \ + .domain = 1, \ + } + +#define FUNCTION(fn) \ + { \ + .name = #fn, \ + .groups = fn ## _groups, \ + .num_groups = ARRAY_SIZE(fn ## _groups), \ + } + +#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ + { \ + .name = n, \ + .first = f, \ + .last = l, \ + .regs = { \ + [REG_PULLEN] = { per, peb }, \ + [REG_PULL] = { pr, pb }, \ + [REG_DIR] = { dr, db }, \ + [REG_OUT] = { or, ob }, \ + [REG_IN] = { ir, ib }, \ + }, \ + } + +#define MESON_PIN(x) PINCTRL_PIN(PIN_ ## x, #x) + +extern struct meson_pinctrl_data meson8_pinctrl_data; diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c new file mode 100644 index 000000000000..f8aa3a281767 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson8.c @@ -0,0 +1,1089 @@ +/* + * Pin controller and GPIO driver for Amlogic Meson8. + * + * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <dt-bindings/gpio/meson8-gpio.h> +#include "pinctrl-meson.h" + +#define AO_OFFSET 120 + +#define PIN_GPIOX_0 GPIOX_0 +#define PIN_GPIOX_1 GPIOX_1 +#define PIN_GPIOX_2 GPIOX_2 +#define PIN_GPIOX_3 GPIOX_3 +#define PIN_GPIOX_4 GPIOX_4 +#define PIN_GPIOX_5 GPIOX_5 +#define PIN_GPIOX_6 GPIOX_6 +#define PIN_GPIOX_7 GPIOX_7 +#define PIN_GPIOX_8 GPIOX_8 +#define PIN_GPIOX_9 GPIOX_9 +#define PIN_GPIOX_10 GPIOX_10 +#define PIN_GPIOX_11 GPIOX_11 +#define PIN_GPIOX_12 GPIOX_12 +#define PIN_GPIOX_13 GPIOX_13 +#define PIN_GPIOX_14 GPIOX_14 +#define PIN_GPIOX_15 GPIOX_15 +#define PIN_GPIOX_16 GPIOX_16 +#define PIN_GPIOX_17 GPIOX_17 +#define PIN_GPIOX_18 GPIOX_18 +#define PIN_GPIOX_19 GPIOX_19 +#define PIN_GPIOX_20 GPIOX_20 +#define PIN_GPIOX_21 GPIOX_21 +#define PIN_GPIOY_0 GPIOY_0 +#define PIN_GPIOY_1 GPIOY_1 +#define PIN_GPIOY_2 GPIOY_2 +#define PIN_GPIOY_3 GPIOY_3 +#define PIN_GPIOY_4 GPIOY_4 +#define PIN_GPIOY_5 GPIOY_5 +#define PIN_GPIOY_6 GPIOY_6 +#define PIN_GPIOY_7 GPIOY_7 +#define PIN_GPIOY_8 GPIOY_8 +#define PIN_GPIOY_9 GPIOY_9 +#define PIN_GPIOY_10 GPIOY_10 +#define PIN_GPIOY_11 GPIOY_11 +#define PIN_GPIOY_12 GPIOY_12 +#define PIN_GPIOY_13 GPIOY_13 +#define PIN_GPIOY_14 GPIOY_14 +#define PIN_GPIOY_15 GPIOY_15 +#define PIN_GPIOY_16 GPIOY_16 +#define PIN_GPIODV_0 GPIODV_0 +#define PIN_GPIODV_1 GPIODV_1 +#define PIN_GPIODV_2 GPIODV_2 +#define PIN_GPIODV_3 GPIODV_3 +#define PIN_GPIODV_4 GPIODV_4 +#define PIN_GPIODV_5 GPIODV_5 +#define PIN_GPIODV_6 GPIODV_6 +#define PIN_GPIODV_7 GPIODV_7 +#define PIN_GPIODV_8 GPIODV_8 +#define PIN_GPIODV_9 GPIODV_9 +#define PIN_GPIODV_10 GPIODV_10 +#define PIN_GPIODV_11 GPIODV_11 +#define PIN_GPIODV_12 GPIODV_12 +#define PIN_GPIODV_13 GPIODV_13 +#define PIN_GPIODV_14 GPIODV_14 +#define PIN_GPIODV_15 GPIODV_15 +#define PIN_GPIODV_16 GPIODV_16 +#define PIN_GPIODV_17 GPIODV_17 +#define PIN_GPIODV_18 GPIODV_18 +#define PIN_GPIODV_19 GPIODV_19 +#define PIN_GPIODV_20 GPIODV_20 +#define PIN_GPIODV_21 GPIODV_21 +#define PIN_GPIODV_22 GPIODV_22 +#define PIN_GPIODV_23 GPIODV_23 +#define PIN_GPIODV_24 GPIODV_24 +#define PIN_GPIODV_25 GPIODV_25 +#define PIN_GPIODV_26 GPIODV_26 +#define PIN_GPIODV_27 GPIODV_27 +#define PIN_GPIODV_28 GPIODV_28 +#define PIN_GPIODV_29 GPIODV_29 +#define PIN_GPIOH_0 GPIOH_0 +#define PIN_GPIOH_1 GPIOH_1 +#define PIN_GPIOH_2 GPIOH_2 +#define PIN_GPIOH_3 GPIOH_3 +#define PIN_GPIOH_4 GPIOH_4 +#define PIN_GPIOH_5 GPIOH_5 +#define PIN_GPIOH_6 GPIOH_6 +#define PIN_GPIOH_7 GPIOH_7 +#define PIN_GPIOH_8 GPIOH_8 +#define PIN_GPIOH_9 GPIOH_9 +#define PIN_GPIOZ_0 GPIOZ_0 +#define PIN_GPIOZ_1 GPIOZ_1 +#define PIN_GPIOZ_2 GPIOZ_2 +#define PIN_GPIOZ_3 GPIOZ_3 +#define PIN_GPIOZ_4 GPIOZ_4 +#define PIN_GPIOZ_5 GPIOZ_5 +#define PIN_GPIOZ_6 GPIOZ_6 +#define PIN_GPIOZ_7 GPIOZ_7 +#define PIN_GPIOZ_8 GPIOZ_8 +#define PIN_GPIOZ_9 GPIOZ_9 +#define PIN_GPIOZ_10 GPIOZ_10 +#define PIN_GPIOZ_11 GPIOZ_11 +#define PIN_GPIOZ_12 GPIOZ_12 +#define PIN_GPIOZ_13 GPIOZ_13 +#define PIN_GPIOZ_14 GPIOZ_14 +#define PIN_CARD_0 CARD_0 +#define PIN_CARD_1 CARD_1 +#define PIN_CARD_2 CARD_2 +#define PIN_CARD_3 CARD_3 +#define PIN_CARD_4 CARD_4 +#define PIN_CARD_5 CARD_5 +#define PIN_CARD_6 CARD_6 +#define PIN_BOOT_0 BOOT_0 +#define PIN_BOOT_1 BOOT_1 +#define PIN_BOOT_2 BOOT_2 +#define PIN_BOOT_3 BOOT_3 +#define PIN_BOOT_4 BOOT_4 +#define PIN_BOOT_5 BOOT_5 +#define PIN_BOOT_6 BOOT_6 +#define PIN_BOOT_7 BOOT_7 +#define PIN_BOOT_8 BOOT_8 +#define PIN_BOOT_9 BOOT_9 +#define PIN_BOOT_10 BOOT_10 +#define PIN_BOOT_11 BOOT_11 +#define PIN_BOOT_12 BOOT_12 +#define PIN_BOOT_13 BOOT_13 +#define PIN_BOOT_14 BOOT_14 +#define PIN_BOOT_15 BOOT_15 +#define PIN_BOOT_16 BOOT_16 +#define PIN_BOOT_17 BOOT_17 +#define PIN_BOOT_18 BOOT_18 + +#define PIN_GPIOAO_0 (AO_OFFSET + GPIOAO_0) +#define PIN_GPIOAO_1 (AO_OFFSET + GPIOAO_1) +#define PIN_GPIOAO_2 (AO_OFFSET + GPIOAO_2) +#define PIN_GPIOAO_3 (AO_OFFSET + GPIOAO_3) +#define PIN_GPIOAO_4 (AO_OFFSET + GPIOAO_4) +#define PIN_GPIOAO_5 (AO_OFFSET + GPIOAO_5) +#define PIN_GPIOAO_6 (AO_OFFSET + GPIOAO_6) +#define PIN_GPIOAO_7 (AO_OFFSET + GPIOAO_7) +#define PIN_GPIOAO_8 (AO_OFFSET + GPIOAO_8) +#define PIN_GPIOAO_9 (AO_OFFSET + GPIOAO_9) +#define PIN_GPIOAO_10 (AO_OFFSET + GPIOAO_10) +#define PIN_GPIOAO_11 (AO_OFFSET + GPIOAO_11) +#define PIN_GPIOAO_12 (AO_OFFSET + GPIOAO_12) +#define PIN_GPIOAO_13 (AO_OFFSET + GPIOAO_13) +#define PIN_GPIO_BSD_EN (AO_OFFSET + GPIO_BSD_EN) +#define PIN_GPIO_TEST_N (AO_OFFSET + GPIO_TEST_N) + +static const struct pinctrl_pin_desc meson8_pins[] = { + MESON_PIN(GPIOX_0), + MESON_PIN(GPIOX_1), + MESON_PIN(GPIOX_2), + MESON_PIN(GPIOX_3), + MESON_PIN(GPIOX_4), + MESON_PIN(GPIOX_5), + MESON_PIN(GPIOX_6), + MESON_PIN(GPIOX_7), + MESON_PIN(GPIOX_8), + MESON_PIN(GPIOX_9), + MESON_PIN(GPIOX_10), + MESON_PIN(GPIOX_11), + MESON_PIN(GPIOX_12), + MESON_PIN(GPIOX_13), + MESON_PIN(GPIOX_14), + MESON_PIN(GPIOX_15), + MESON_PIN(GPIOX_16), + MESON_PIN(GPIOX_17), + MESON_PIN(GPIOX_18), + MESON_PIN(GPIOX_19), + MESON_PIN(GPIOX_20), + MESON_PIN(GPIOX_21), + MESON_PIN(GPIOY_0), + MESON_PIN(GPIOY_1), + MESON_PIN(GPIOY_2), + MESON_PIN(GPIOY_3), + MESON_PIN(GPIOY_4), + MESON_PIN(GPIOY_5), + MESON_PIN(GPIOY_6), + MESON_PIN(GPIOY_7), + MESON_PIN(GPIOY_8), + MESON_PIN(GPIOY_9), + MESON_PIN(GPIOY_10), + MESON_PIN(GPIOY_11), + MESON_PIN(GPIOY_12), + MESON_PIN(GPIOY_13), + MESON_PIN(GPIOY_14), + MESON_PIN(GPIOY_15), + MESON_PIN(GPIOY_16), + MESON_PIN(GPIODV_0), + MESON_PIN(GPIODV_1), + MESON_PIN(GPIODV_2), + MESON_PIN(GPIODV_3), + MESON_PIN(GPIODV_4), + MESON_PIN(GPIODV_5), + MESON_PIN(GPIODV_6), + MESON_PIN(GPIODV_7), + MESON_PIN(GPIODV_8), + MESON_PIN(GPIODV_9), + MESON_PIN(GPIODV_10), + MESON_PIN(GPIODV_11), + MESON_PIN(GPIODV_12), + MESON_PIN(GPIODV_13), + MESON_PIN(GPIODV_14), + MESON_PIN(GPIODV_15), + MESON_PIN(GPIODV_16), + MESON_PIN(GPIODV_17), + MESON_PIN(GPIODV_18), + MESON_PIN(GPIODV_19), + MESON_PIN(GPIODV_20), + MESON_PIN(GPIODV_21), + MESON_PIN(GPIODV_22), + MESON_PIN(GPIODV_23), + MESON_PIN(GPIODV_24), + MESON_PIN(GPIODV_25), + MESON_PIN(GPIODV_26), + MESON_PIN(GPIODV_27), + MESON_PIN(GPIODV_28), + MESON_PIN(GPIODV_29), + MESON_PIN(GPIOH_0), + MESON_PIN(GPIOH_1), + MESON_PIN(GPIOH_2), + MESON_PIN(GPIOH_3), + MESON_PIN(GPIOH_4), + MESON_PIN(GPIOH_5), + MESON_PIN(GPIOH_6), + MESON_PIN(GPIOH_7), + MESON_PIN(GPIOH_8), + MESON_PIN(GPIOH_9), + MESON_PIN(GPIOZ_0), + MESON_PIN(GPIOZ_1), + MESON_PIN(GPIOZ_2), + MESON_PIN(GPIOZ_3), + MESON_PIN(GPIOZ_4), + MESON_PIN(GPIOZ_5), + MESON_PIN(GPIOZ_6), + MESON_PIN(GPIOZ_7), + MESON_PIN(GPIOZ_8), + MESON_PIN(GPIOZ_9), + MESON_PIN(GPIOZ_10), + MESON_PIN(GPIOZ_11), + MESON_PIN(GPIOZ_12), + MESON_PIN(GPIOZ_13), + MESON_PIN(GPIOZ_14), + MESON_PIN(CARD_0), + MESON_PIN(CARD_1), + MESON_PIN(CARD_2), + MESON_PIN(CARD_3), + MESON_PIN(CARD_4), + MESON_PIN(CARD_5), + MESON_PIN(CARD_6), + MESON_PIN(BOOT_0), + MESON_PIN(BOOT_1), + MESON_PIN(BOOT_2), + MESON_PIN(BOOT_3), + MESON_PIN(BOOT_4), + MESON_PIN(BOOT_5), + MESON_PIN(BOOT_6), + MESON_PIN(BOOT_7), + MESON_PIN(BOOT_8), + MESON_PIN(BOOT_9), + MESON_PIN(BOOT_10), + MESON_PIN(BOOT_11), + MESON_PIN(BOOT_12), + MESON_PIN(BOOT_13), + MESON_PIN(BOOT_14), + MESON_PIN(BOOT_15), + MESON_PIN(BOOT_16), + MESON_PIN(BOOT_17), + MESON_PIN(BOOT_18), + MESON_PIN(GPIOAO_0), + MESON_PIN(GPIOAO_1), + MESON_PIN(GPIOAO_2), + MESON_PIN(GPIOAO_3), + MESON_PIN(GPIOAO_4), + MESON_PIN(GPIOAO_5), + MESON_PIN(GPIOAO_6), + MESON_PIN(GPIOAO_7), + MESON_PIN(GPIOAO_8), + MESON_PIN(GPIOAO_9), + MESON_PIN(GPIOAO_10), + MESON_PIN(GPIOAO_11), + MESON_PIN(GPIOAO_12), + MESON_PIN(GPIOAO_13), + MESON_PIN(GPIO_BSD_EN), + MESON_PIN(GPIO_TEST_N), +}; + +/* bank X */ +static const unsigned int sd_d0_a_pins[] = { PIN_GPIOX_0 }; +static const unsigned int sd_d1_a_pins[] = { PIN_GPIOX_1 }; +static const unsigned int sd_d2_a_pins[] = { PIN_GPIOX_2 }; +static const unsigned int sd_d3_a_pins[] = { PIN_GPIOX_3 }; +static const unsigned int sd_clk_a_pins[] = { PIN_GPIOX_8 }; +static const unsigned int sd_cmd_a_pins[] = { PIN_GPIOX_9 }; + +static const unsigned int sdxc_d0_a_pins[] = { PIN_GPIOX_0 }; +static const unsigned int sdxc_d13_a_pins[] = { PIN_GPIOX_1, PIN_GPIOX_2, + PIN_GPIOX_3 }; +static const unsigned int sdxc_d47_a_pins[] = { PIN_GPIOX_4, PIN_GPIOX_5, + PIN_GPIOX_6, PIN_GPIOX_7 }; +static const unsigned int sdxc_clk_a_pins[] = { PIN_GPIOX_8 }; +static const unsigned int sdxc_cmd_a_pins[] = { PIN_GPIOX_9 }; + +static const unsigned int pcm_out_a_pins[] = { PIN_GPIOX_4 }; +static const unsigned int pcm_in_a_pins[] = { PIN_GPIOX_5 }; +static const unsigned int pcm_fs_a_pins[] = { PIN_GPIOX_6 }; +static const unsigned int pcm_clk_a_pins[] = { PIN_GPIOX_7 }; + +static const unsigned int uart_tx_a0_pins[] = { PIN_GPIOX_4 }; +static const unsigned int uart_rx_a0_pins[] = { PIN_GPIOX_5 }; +static const unsigned int uart_cts_a0_pins[] = { PIN_GPIOX_6 }; +static const unsigned int uart_rts_a0_pins[] = { PIN_GPIOX_7 }; + +static const unsigned int uart_tx_a1_pins[] = { PIN_GPIOX_12 }; +static const unsigned int uart_rx_a1_pins[] = { PIN_GPIOX_13 }; +static const unsigned int uart_cts_a1_pins[] = { PIN_GPIOX_14 }; +static const unsigned int uart_rts_a1_pins[] = { PIN_GPIOX_15 }; + +static const unsigned int uart_tx_b0_pins[] = { PIN_GPIOX_16 }; +static const unsigned int uart_rx_b0_pins[] = { PIN_GPIOX_17 }; +static const unsigned int uart_cts_b0_pins[] = { PIN_GPIOX_18 }; +static const unsigned int uart_rts_b0_pins[] = { PIN_GPIOX_19 }; + +static const unsigned int iso7816_det_pins[] = { PIN_GPIOX_16 }; +static const unsigned int iso7816_reset_pins[] = { PIN_GPIOX_17 }; +static const unsigned int iso7816_clk_pins[] = { PIN_GPIOX_18 }; +static const unsigned int iso7816_data_pins[] = { PIN_GPIOX_19 }; + +static const unsigned int i2c_sda_d0_pins[] = { PIN_GPIOX_16 }; +static const unsigned int i2c_sck_d0_pins[] = { PIN_GPIOX_17 }; + +static const unsigned int xtal_32k_out_pins[] = { PIN_GPIOX_10 }; +static const unsigned int xtal_24m_out_pins[] = { PIN_GPIOX_11 }; + +/* bank Y */ +static const unsigned int uart_tx_c_pins[] = { PIN_GPIOY_0 }; +static const unsigned int uart_rx_c_pins[] = { PIN_GPIOY_1 }; +static const unsigned int uart_cts_c_pins[] = { PIN_GPIOY_2 }; +static const unsigned int uart_rts_c_pins[] = { PIN_GPIOY_3 }; + +static const unsigned int pcm_out_b_pins[] = { PIN_GPIOY_4 }; +static const unsigned int pcm_in_b_pins[] = { PIN_GPIOY_5 }; +static const unsigned int pcm_fs_b_pins[] = { PIN_GPIOY_6 }; +static const unsigned int pcm_clk_b_pins[] = { PIN_GPIOY_7 }; + +static const unsigned int i2c_sda_c0_pins[] = { PIN_GPIOY_0 }; +static const unsigned int i2c_sck_c0_pins[] = { PIN_GPIOY_1 }; + +/* bank DV */ +static const unsigned int dvin_rgb_pins[] = { PIN_GPIODV_0, PIN_GPIODV_1, + PIN_GPIODV_2, PIN_GPIODV_3, + PIN_GPIODV_4, PIN_GPIODV_5, + PIN_GPIODV_6, PIN_GPIODV_7, + PIN_GPIODV_8, PIN_GPIODV_9, + PIN_GPIODV_10, PIN_GPIODV_11, + PIN_GPIODV_12, PIN_GPIODV_13, + PIN_GPIODV_14, PIN_GPIODV_15, + PIN_GPIODV_16, PIN_GPIODV_17, + PIN_GPIODV_18, PIN_GPIODV_19, + PIN_GPIODV_20, PIN_GPIODV_21, + PIN_GPIODV_22, PIN_GPIODV_23 }; +static const unsigned int dvin_vs_pins[] = { PIN_GPIODV_24 }; +static const unsigned int dvin_hs_pins[] = { PIN_GPIODV_25 }; +static const unsigned int dvin_clk_pins[] = { PIN_GPIODV_26 }; +static const unsigned int dvin_de_pins[] = { PIN_GPIODV_27 }; + +static const unsigned int enc_0_pins[] = { PIN_GPIODV_0 }; +static const unsigned int enc_1_pins[] = { PIN_GPIODV_1 }; +static const unsigned int enc_2_pins[] = { PIN_GPIODV_2 }; +static const unsigned int enc_3_pins[] = { PIN_GPIODV_3 }; +static const unsigned int enc_4_pins[] = { PIN_GPIODV_4 }; +static const unsigned int enc_5_pins[] = { PIN_GPIODV_5 }; +static const unsigned int enc_6_pins[] = { PIN_GPIODV_6 }; +static const unsigned int enc_7_pins[] = { PIN_GPIODV_7 }; +static const unsigned int enc_8_pins[] = { PIN_GPIODV_8 }; +static const unsigned int enc_9_pins[] = { PIN_GPIODV_9 }; +static const unsigned int enc_10_pins[] = { PIN_GPIODV_10 }; +static const unsigned int enc_11_pins[] = { PIN_GPIODV_11 }; +static const unsigned int enc_12_pins[] = { PIN_GPIODV_12 }; +static const unsigned int enc_13_pins[] = { PIN_GPIODV_13 }; +static const unsigned int enc_14_pins[] = { PIN_GPIODV_14 }; +static const unsigned int enc_15_pins[] = { PIN_GPIODV_15 }; +static const unsigned int enc_16_pins[] = { PIN_GPIODV_16 }; +static const unsigned int enc_17_pins[] = { PIN_GPIODV_17 }; + +static const unsigned int uart_tx_b1_pins[] = { PIN_GPIODV_24 }; +static const unsigned int uart_rx_b1_pins[] = { PIN_GPIODV_25 }; +static const unsigned int uart_cts_b1_pins[] = { PIN_GPIODV_26 }; +static const unsigned int uart_rts_b1_pins[] = { PIN_GPIODV_27 }; + +static const unsigned int vga_vs_pins[] = { PIN_GPIODV_24 }; +static const unsigned int vga_hs_pins[] = { PIN_GPIODV_25 }; + +/* bank H */ +static const unsigned int hdmi_hpd_pins[] = { PIN_GPIOH_0 }; +static const unsigned int hdmi_sda_pins[] = { PIN_GPIOH_1 }; +static const unsigned int hdmi_scl_pins[] = { PIN_GPIOH_2 }; +static const unsigned int hdmi_cec_pins[] = { PIN_GPIOH_3 }; + +static const unsigned int spi_ss0_0_pins[] = { PIN_GPIOH_3 }; +static const unsigned int spi_miso_0_pins[] = { PIN_GPIOH_4 }; +static const unsigned int spi_mosi_0_pins[] = { PIN_GPIOH_5 }; +static const unsigned int spi_sclk_0_pins[] = { PIN_GPIOH_6 }; + +static const unsigned int i2c_sda_d1_pins[] = { PIN_GPIOH_7 }; +static const unsigned int i2c_sck_d1_pins[] = { PIN_GPIOH_8 }; + +/* bank Z */ +static const unsigned int spi_ss0_1_pins[] = { PIN_GPIOZ_9 }; +static const unsigned int spi_ss1_1_pins[] = { PIN_GPIOZ_10 }; +static const unsigned int spi_sclk_1_pins[] = { PIN_GPIOZ_11 }; +static const unsigned int spi_mosi_1_pins[] = { PIN_GPIOZ_12 }; +static const unsigned int spi_miso_1_pins[] = { PIN_GPIOZ_13 }; +static const unsigned int spi_ss2_1_pins[] = { PIN_GPIOZ_14 }; + +static const unsigned int eth_tx_clk_50m_pins[] = { PIN_GPIOZ_4 }; +static const unsigned int eth_tx_en_pins[] = { PIN_GPIOZ_5 }; +static const unsigned int eth_txd1_pins[] = { PIN_GPIOZ_6 }; +static const unsigned int eth_txd0_pins[] = { PIN_GPIOZ_7 }; +static const unsigned int eth_rx_clk_in_pins[] = { PIN_GPIOZ_8 }; +static const unsigned int eth_rx_dv_pins[] = { PIN_GPIOZ_9 }; +static const unsigned int eth_rxd1_pins[] = { PIN_GPIOZ_10 }; +static const unsigned int eth_rxd0_pins[] = { PIN_GPIOZ_11 }; +static const unsigned int eth_mdio_pins[] = { PIN_GPIOZ_12 }; +static const unsigned int eth_mdc_pins[] = { PIN_GPIOZ_13 }; + +static const unsigned int i2c_sda_a0_pins[] = { PIN_GPIOZ_0 }; +static const unsigned int i2c_sck_a0_pins[] = { PIN_GPIOZ_1 }; + +static const unsigned int i2c_sda_b_pins[] = { PIN_GPIOZ_2 }; +static const unsigned int i2c_sck_b_pins[] = { PIN_GPIOZ_3 }; + +static const unsigned int i2c_sda_c1_pins[] = { PIN_GPIOZ_4 }; +static const unsigned int i2c_sck_c1_pins[] = { PIN_GPIOZ_5 }; + +static const unsigned int i2c_sda_a1_pins[] = { PIN_GPIOZ_0 }; +static const unsigned int i2c_sck_a1_pins[] = { PIN_GPIOZ_1 }; + +static const unsigned int i2c_sda_a2_pins[] = { PIN_GPIOZ_0 }; +static const unsigned int i2c_sck_a2_pins[] = { PIN_GPIOZ_1 }; + +/* bank BOOT */ +static const unsigned int sd_d0_c_pins[] = { PIN_BOOT_0 }; +static const unsigned int sd_d1_c_pins[] = { PIN_BOOT_1 }; +static const unsigned int sd_d2_c_pins[] = { PIN_BOOT_2 }; +static const unsigned int sd_d3_c_pins[] = { PIN_BOOT_3 }; +static const unsigned int sd_cmd_c_pins[] = { PIN_BOOT_16 }; +static const unsigned int sd_clk_c_pins[] = { PIN_BOOT_17 }; + +static const unsigned int sdxc_d0_c_pins[] = { PIN_BOOT_0}; +static const unsigned int sdxc_d13_c_pins[] = { PIN_BOOT_1, PIN_BOOT_2, + PIN_BOOT_3 }; +static const unsigned int sdxc_d47_c_pins[] = { PIN_BOOT_4, PIN_BOOT_5, + PIN_BOOT_6, PIN_BOOT_7 }; +static const unsigned int sdxc_cmd_c_pins[] = { PIN_BOOT_16 }; +static const unsigned int sdxc_clk_c_pins[] = { PIN_BOOT_17 }; + +static const unsigned int nand_io_pins[] = { PIN_BOOT_0, PIN_BOOT_1, + PIN_BOOT_2, PIN_BOOT_3, + PIN_BOOT_4, PIN_BOOT_5, + PIN_BOOT_6, PIN_BOOT_7 }; +static const unsigned int nand_io_ce0_pins[] = { PIN_BOOT_8 }; +static const unsigned int nand_io_ce1_pins[] = { PIN_BOOT_9 }; +static const unsigned int nand_io_rb0_pins[] = { PIN_BOOT_10 }; +static const unsigned int nand_ale_pins[] = { PIN_BOOT_11 }; +static const unsigned int nand_cle_pins[] = { PIN_BOOT_12 }; +static const unsigned int nand_wen_clk_pins[] = { PIN_BOOT_13 }; +static const unsigned int nand_ren_clk_pins[] = { PIN_BOOT_14 }; +static const unsigned int nand_dqs_pins[] = { PIN_BOOT_15 }; +static const unsigned int nand_ce2_pins[] = { PIN_BOOT_16 }; +static const unsigned int nand_ce3_pins[] = { PIN_BOOT_17 }; + +static const unsigned int nor_d_pins[] = { PIN_BOOT_11 }; +static const unsigned int nor_q_pins[] = { PIN_BOOT_12 }; +static const unsigned int nor_c_pins[] = { PIN_BOOT_13 }; +static const unsigned int nor_cs_pins[] = { PIN_BOOT_18 }; + +/* bank CARD */ +static const unsigned int sd_d1_b_pins[] = { PIN_CARD_0 }; +static const unsigned int sd_d0_b_pins[] = { PIN_CARD_1 }; +static const unsigned int sd_clk_b_pins[] = { PIN_CARD_2 }; +static const unsigned int sd_cmd_b_pins[] = { PIN_CARD_3 }; +static const unsigned int sd_d3_b_pins[] = { PIN_CARD_4 }; +static const unsigned int sd_d2_b_pins[] = { PIN_CARD_5 }; + +static const unsigned int sdxc_d13_b_pins[] = { PIN_CARD_0, PIN_CARD_4, + PIN_CARD_5 }; +static const unsigned int sdxc_d0_b_pins[] = { PIN_CARD_1 }; +static const unsigned int sdxc_clk_b_pins[] = { PIN_CARD_2 }; +static const unsigned int sdxc_cmd_b_pins[] = { PIN_CARD_3 }; + +/* bank AO */ +static const unsigned int uart_tx_ao_a_pins[] = { PIN_GPIOAO_0 }; +static const unsigned int uart_rx_ao_a_pins[] = { PIN_GPIOAO_1 }; +static const unsigned int uart_cts_ao_a_pins[] = { PIN_GPIOAO_2 }; +static const unsigned int uart_rts_ao_a_pins[] = { PIN_GPIOAO_3 }; + +static const unsigned int remote_input_pins[] = { PIN_GPIOAO_7 }; + +static const unsigned int i2c_slave_sck_ao_pins[] = { PIN_GPIOAO_4 }; +static const unsigned int i2c_slave_sda_ao_pins[] = { PIN_GPIOAO_5 }; + +static const unsigned int uart_tx_ao_b0_pins[] = { PIN_GPIOAO_0 }; +static const unsigned int uart_rx_ao_b0_pins[] = { PIN_GPIOAO_1 }; + +static const unsigned int uart_tx_ao_b1_pins[] = { PIN_GPIOAO_4 }; +static const unsigned int uart_rx_ao_b1_pins[] = { PIN_GPIOAO_5 }; + +static const unsigned int i2c_mst_sck_ao_pins[] = { PIN_GPIOAO_4 }; +static const unsigned int i2c_mst_sda_ao_pins[] = { PIN_GPIOAO_5 }; + +static struct meson_pmx_group meson8_groups[] = { + GPIO_GROUP(GPIOX_0), + GPIO_GROUP(GPIOX_1), + GPIO_GROUP(GPIOX_2), + GPIO_GROUP(GPIOX_3), + GPIO_GROUP(GPIOX_4), + GPIO_GROUP(GPIOX_5), + GPIO_GROUP(GPIOX_6), + GPIO_GROUP(GPIOX_7), + GPIO_GROUP(GPIOX_8), + GPIO_GROUP(GPIOX_9), + GPIO_GROUP(GPIOX_10), + GPIO_GROUP(GPIOX_11), + GPIO_GROUP(GPIOX_12), + GPIO_GROUP(GPIOX_13), + GPIO_GROUP(GPIOX_14), + GPIO_GROUP(GPIOX_15), + GPIO_GROUP(GPIOX_16), + GPIO_GROUP(GPIOX_17), + GPIO_GROUP(GPIOX_18), + GPIO_GROUP(GPIOX_19), + GPIO_GROUP(GPIOX_20), + GPIO_GROUP(GPIOX_21), + GPIO_GROUP(GPIOY_0), + GPIO_GROUP(GPIOY_1), + GPIO_GROUP(GPIOY_2), + GPIO_GROUP(GPIOY_3), + GPIO_GROUP(GPIOY_4), + GPIO_GROUP(GPIOY_5), + GPIO_GROUP(GPIOY_6), + GPIO_GROUP(GPIOY_7), + GPIO_GROUP(GPIOY_8), + GPIO_GROUP(GPIOY_9), + GPIO_GROUP(GPIOY_10), + GPIO_GROUP(GPIOY_11), + GPIO_GROUP(GPIOY_12), + GPIO_GROUP(GPIOY_13), + GPIO_GROUP(GPIOY_14), + GPIO_GROUP(GPIOY_15), + GPIO_GROUP(GPIOY_16), + GPIO_GROUP(GPIODV_0), + GPIO_GROUP(GPIODV_1), + GPIO_GROUP(GPIODV_2), + GPIO_GROUP(GPIODV_3), + GPIO_GROUP(GPIODV_4), + GPIO_GROUP(GPIODV_5), + GPIO_GROUP(GPIODV_6), + GPIO_GROUP(GPIODV_7), + GPIO_GROUP(GPIODV_8), + GPIO_GROUP(GPIODV_9), + GPIO_GROUP(GPIODV_10), + GPIO_GROUP(GPIODV_11), + GPIO_GROUP(GPIODV_12), + GPIO_GROUP(GPIODV_13), + GPIO_GROUP(GPIODV_14), + GPIO_GROUP(GPIODV_15), + GPIO_GROUP(GPIODV_16), + GPIO_GROUP(GPIODV_17), + GPIO_GROUP(GPIODV_18), + GPIO_GROUP(GPIODV_19), + GPIO_GROUP(GPIODV_20), + GPIO_GROUP(GPIODV_21), + GPIO_GROUP(GPIODV_22), + GPIO_GROUP(GPIODV_23), + GPIO_GROUP(GPIODV_24), + GPIO_GROUP(GPIODV_25), + GPIO_GROUP(GPIODV_26), + GPIO_GROUP(GPIODV_27), + GPIO_GROUP(GPIODV_28), + GPIO_GROUP(GPIODV_29), + GPIO_GROUP(GPIOH_0), + GPIO_GROUP(GPIOH_1), + GPIO_GROUP(GPIOH_2), + GPIO_GROUP(GPIOH_3), + GPIO_GROUP(GPIOH_4), + GPIO_GROUP(GPIOH_5), + GPIO_GROUP(GPIOH_6), + GPIO_GROUP(GPIOH_7), + GPIO_GROUP(GPIOH_8), + GPIO_GROUP(GPIOH_9), + GPIO_GROUP(GPIOZ_0), + GPIO_GROUP(GPIOZ_1), + GPIO_GROUP(GPIOZ_2), + GPIO_GROUP(GPIOZ_3), + GPIO_GROUP(GPIOZ_4), + GPIO_GROUP(GPIOZ_5), + GPIO_GROUP(GPIOZ_6), + GPIO_GROUP(GPIOZ_7), + GPIO_GROUP(GPIOZ_8), + GPIO_GROUP(GPIOZ_9), + GPIO_GROUP(GPIOZ_10), + GPIO_GROUP(GPIOZ_11), + GPIO_GROUP(GPIOZ_12), + GPIO_GROUP(GPIOZ_13), + GPIO_GROUP(GPIOZ_14), + GPIO_GROUP(GPIOAO_0), + GPIO_GROUP(GPIOAO_1), + GPIO_GROUP(GPIOAO_2), + GPIO_GROUP(GPIOAO_3), + GPIO_GROUP(GPIOAO_4), + GPIO_GROUP(GPIOAO_5), + GPIO_GROUP(GPIOAO_6), + GPIO_GROUP(GPIOAO_7), + GPIO_GROUP(GPIOAO_8), + GPIO_GROUP(GPIOAO_9), + GPIO_GROUP(GPIOAO_10), + GPIO_GROUP(GPIOAO_11), + GPIO_GROUP(GPIOAO_12), + GPIO_GROUP(GPIOAO_13), + GPIO_GROUP(GPIO_BSD_EN), + GPIO_GROUP(GPIO_TEST_N), + + /* bank X */ + GROUP(sd_d0_a, 8, 5), + GROUP(sd_d1_a, 8, 4), + GROUP(sd_d2_a, 8, 3), + GROUP(sd_d3_a, 8, 2), + GROUP(sd_clk_a, 8, 1), + GROUP(sd_cmd_a, 8, 0), + + GROUP(sdxc_d0_a, 5, 14), + GROUP(sdxc_d13_a, 5, 13), + GROUP(sdxc_d47_a, 5, 12), + GROUP(sdxc_clk_a, 5, 11), + GROUP(sdxc_cmd_a, 5, 10), + + GROUP(pcm_out_a, 3, 30), + GROUP(pcm_in_a, 3, 29), + GROUP(pcm_fs_a, 3, 28), + GROUP(pcm_clk_a, 3, 27), + + GROUP(uart_tx_a0, 4, 17), + GROUP(uart_rx_a0, 4, 16), + GROUP(uart_cts_a0, 4, 15), + GROUP(uart_rts_a0, 4, 14), + + GROUP(uart_tx_a1, 4, 13), + GROUP(uart_rx_a1, 4, 12), + GROUP(uart_cts_a1, 4, 11), + GROUP(uart_rts_a1, 4, 10), + + GROUP(uart_tx_b0, 4, 9), + GROUP(uart_rx_b0, 4, 8), + GROUP(uart_cts_b0, 4, 7), + GROUP(uart_rts_b0, 4, 6), + + GROUP(iso7816_det, 4, 21), + GROUP(iso7816_reset, 4, 20), + GROUP(iso7816_clk, 4, 19), + GROUP(iso7816_data, 4, 18), + + GROUP(i2c_sda_d0, 4, 5), + GROUP(i2c_sck_d0, 4, 4), + + GROUP(xtal_32k_out, 3, 22), + GROUP(xtal_24m_out, 3, 23), + + /* bank Y */ + GROUP(uart_tx_c, 1, 19), + GROUP(uart_rx_c, 1, 18), + GROUP(uart_cts_c, 1, 17), + GROUP(uart_rts_c, 1, 16), + + GROUP(pcm_out_b, 4, 25), + GROUP(pcm_in_b, 4, 24), + GROUP(pcm_fs_b, 4, 23), + GROUP(pcm_clk_b, 4, 22), + + GROUP(i2c_sda_c0, 1, 15), + GROUP(i2c_sck_c0, 1, 14), + + /* bank DV */ + GROUP(dvin_rgb, 0, 6), + GROUP(dvin_vs, 0, 9), + GROUP(dvin_hs, 0, 8), + GROUP(dvin_clk, 0, 7), + GROUP(dvin_de, 0, 10), + + GROUP(enc_0, 7, 0), + GROUP(enc_1, 7, 1), + GROUP(enc_2, 7, 2), + GROUP(enc_3, 7, 3), + GROUP(enc_4, 7, 4), + GROUP(enc_5, 7, 5), + GROUP(enc_6, 7, 6), + GROUP(enc_7, 7, 7), + GROUP(enc_8, 7, 8), + GROUP(enc_9, 7, 9), + GROUP(enc_10, 7, 10), + GROUP(enc_11, 7, 11), + GROUP(enc_12, 7, 12), + GROUP(enc_13, 7, 13), + GROUP(enc_14, 7, 14), + GROUP(enc_15, 7, 15), + GROUP(enc_16, 7, 16), + GROUP(enc_17, 7, 17), + + GROUP(uart_tx_b1, 6, 23), + GROUP(uart_rx_b1, 6, 22), + GROUP(uart_cts_b1, 6, 21), + GROUP(uart_rts_b1, 6, 20), + + GROUP(vga_vs, 0, 21), + GROUP(vga_hs, 0, 20), + + /* bank H */ + GROUP(hdmi_hpd, 1, 26), + GROUP(hdmi_sda, 1, 25), + GROUP(hdmi_scl, 1, 24), + GROUP(hdmi_cec, 1, 23), + + GROUP(spi_ss0_0, 9, 13), + GROUP(spi_miso_0, 9, 12), + GROUP(spi_mosi_0, 9, 11), + GROUP(spi_sclk_0, 9, 10), + + GROUP(i2c_sda_d1, 4, 3), + GROUP(i2c_sck_d1, 4, 2), + + /* bank Z */ + GROUP(spi_ss0_1, 8, 16), + GROUP(spi_ss1_1, 8, 12), + GROUP(spi_sclk_1, 8, 15), + GROUP(spi_mosi_1, 8, 14), + GROUP(spi_miso_1, 8, 13), + GROUP(spi_ss2_1, 8, 17), + + GROUP(eth_tx_clk_50m, 6, 15), + GROUP(eth_tx_en, 6, 14), + GROUP(eth_txd1, 6, 13), + GROUP(eth_txd0, 6, 12), + GROUP(eth_rx_clk_in, 6, 10), + GROUP(eth_rx_dv, 6, 11), + GROUP(eth_rxd1, 6, 8), + GROUP(eth_rxd0, 6, 7), + GROUP(eth_mdio, 6, 6), + GROUP(eth_mdc, 6, 5), + + GROUP(i2c_sda_a0, 5, 31), + GROUP(i2c_sck_a0, 5, 30), + + GROUP(i2c_sda_b, 5, 27), + GROUP(i2c_sck_b, 5, 26), + + GROUP(i2c_sda_c1, 5, 25), + GROUP(i2c_sck_c1, 5, 24), + + GROUP(i2c_sda_a1, 5, 9), + GROUP(i2c_sck_a1, 5, 8), + + GROUP(i2c_sda_a2, 5, 7), + GROUP(i2c_sck_a2, 5, 6), + + /* bank BOOT */ + GROUP(sd_d0_c, 6, 29), + GROUP(sd_d1_c, 6, 28), + GROUP(sd_d2_c, 6, 27), + GROUP(sd_d3_c, 6, 26), + GROUP(sd_cmd_c, 6, 25), + GROUP(sd_clk_c, 6, 24), + + GROUP(sdxc_d0_c, 4, 30), + GROUP(sdxc_d13_c, 4, 29), + GROUP(sdxc_d47_c, 4, 28), + GROUP(sdxc_cmd_c, 4, 27), + GROUP(sdxc_clk_c, 4, 26), + + GROUP(nand_io, 2, 26), + GROUP(nand_io_ce0, 2, 25), + GROUP(nand_io_ce1, 2, 24), + GROUP(nand_io_rb0, 2, 17), + GROUP(nand_ale, 2, 21), + GROUP(nand_cle, 2, 20), + GROUP(nand_wen_clk, 2, 19), + GROUP(nand_ren_clk, 2, 18), + GROUP(nand_dqs, 2, 27), + GROUP(nand_ce2, 2, 23), + GROUP(nand_ce3, 2, 22), + + GROUP(nor_d, 5, 1), + GROUP(nor_q, 5, 3), + GROUP(nor_c, 5, 2), + GROUP(nor_cs, 5, 0), + + /* bank CARD */ + GROUP(sd_d1_b, 2, 14), + GROUP(sd_d0_b, 2, 15), + GROUP(sd_clk_b, 2, 11), + GROUP(sd_cmd_b, 2, 10), + GROUP(sd_d3_b, 2, 12), + GROUP(sd_d2_b, 2, 13), + + GROUP(sdxc_d13_b, 2, 6), + GROUP(sdxc_d0_b, 2, 7), + GROUP(sdxc_clk_b, 2, 5), + GROUP(sdxc_cmd_b, 2, 4), + + /* bank AO */ + GROUP_AO(uart_tx_ao_a, 0, 12), + GROUP_AO(uart_rx_ao_a, 0, 11), + GROUP_AO(uart_cts_ao_a, 0, 10), + GROUP_AO(uart_rts_ao_a, 0, 9), + + GROUP_AO(remote_input, 0, 0), + + GROUP_AO(i2c_slave_sck_ao, 0, 2), + GROUP_AO(i2c_slave_sda_ao, 0, 1), + + GROUP_AO(uart_tx_ao_b0, 0, 26), + GROUP_AO(uart_rx_ao_b0, 0, 25), + + GROUP_AO(uart_tx_ao_b1, 0, 24), + GROUP_AO(uart_rx_ao_b1, 0, 23), + + GROUP_AO(i2c_mst_sck_ao, 0, 6), + GROUP_AO(i2c_mst_sda_ao, 0, 5), +}; + +static const char * const gpio_groups[] = { + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", + "GPIOX_20", "GPIOX_21", + + "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4", + "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9", + "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14", + "GPIOY_15", "GPIOY_16", + + "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4", + "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9", + "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14", + "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19", + "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24", + "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29", + + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", + + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", + "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14", + + "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4", + "CARD_5", "CARD_6", + + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", + "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18", + + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", + "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", + "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11", + "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N" +}; + +static const char * const sd_a_groups[] = { + "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", "sd_cmd_a" +}; + +static const char * const sdxc_a_groups[] = { + "sdxc_d0_a", "sdxc_d13_a", "sdxc_d47_a", "sdxc_clk_a", "sdxc_cmd_a" +}; + +static const char * const pcm_a_groups[] = { + "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a" +}; + +static const char * const uart_a_groups[] = { + "uart_tx_a0", "uart_rx_a0", "uart_cts_a0", "uart_rts_a0", + "uart_tx_a1", "uart_rx_a1", "uart_cts_a1", "uart_rts_a1" +}; + +static const char * const uart_b_groups[] = { + "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0", + "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1" +}; + +static const char * const iso7816_groups[] = { + "iso7816_det", "iso7816_reset", "iso7816_clk", "iso7816_data" +}; + +static const char * const i2c_d_groups[] = { + "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1" +}; + +static const char * const xtal_groups[] = { + "xtal_32k_out", "xtal_24m_out" +}; + +static const char * const uart_c_groups[] = { + "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c" +}; + +static const char * const pcm_b_groups[] = { + "pcm_out_b", "pcm_in_b", "pcm_fs_b", "pcm_clk_b" +}; + +static const char * const i2c_c_groups[] = { + "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1" +}; + +static const char * const dvin_groups[] = { + "dvin_rgb", "dvin_vs", "dvin_hs", "dvin_clk", "dvin_de" +}; + +static const char * const enc_groups[] = { + "enc_0", "enc_1", "enc_2", "enc_3", "enc_4", "enc_5", + "enc_6", "enc_7", "enc_8", "enc_9", "enc_10", "enc_11", + "enc_12", "enc_13", "enc_14", "enc_15", "enc_16", "enc_17" +}; + +static const char * const vga_groups[] = { + "vga_vs", "vga_hs" +}; + +static const char * const hdmi_groups[] = { + "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec" +}; + +static const char * const spi_groups[] = { + "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0", + "spi_ss0_1", "spi_ss1_1", "spi_sclk_1", "spi_mosi_1", + "spi_miso_1", "spi_ss2_1" +}; + +static const char * const ethernet_groups[] = { + "eth_tx_clk_50m", "eth_tx_en", "eth_txd1", + "eth_txd0", "eth_rx_clk_in", "eth_rx_dv", + "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc" +}; + +static const char * const i2c_a_groups[] = { + "i2c_sda_a0", "i2c_sck_a0", "i2c_sda_a1", "i2c_sck_a1", + "i2c_sda_a2", "i2c_sck_a2" +}; + +static const char * const i2c_b_groups[] = { + "i2c_sda_b", "i2c_sck_b" +}; + +static const char * const sd_c_groups[] = { + "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c", + "sd_cmd_c", "sd_clk_c" +}; + +static const char * const sdxc_c_groups[] = { + "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c", + "sdxc_clk_c" +}; + +static const char * const nand_groups[] = { + "nand_io", "nand_io_ce0", "nand_io_ce1", + "nand_io_rb0", "nand_ale", "nand_cle", + "nand_wen_clk", "nand_ren_clk", "nand_dqs", + "nand_ce2", "nand_ce3" +}; + +static const char * const nor_groups[] = { + "nor_d", "nor_q", "nor_c", "nor_cs" +}; + +static const char * const sd_b_groups[] = { + "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b", + "sd_d3_b", "sd_d2_b" +}; + +static const char * const sdxc_b_groups[] = { + "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b" +}; + +static const char * const uart_ao_groups[] = { + "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a" +}; + +static const char * const remote_groups[] = { + "remote_input" +}; + +static const char * const i2c_slave_ao_groups[] = { + "i2c_slave_sck_ao", "i2c_slave_sda_ao" +}; + +static const char * const uart_ao_b_groups[] = { + "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1" +}; + +static const char * const i2c_mst_ao_groups[] = { + "i2c_mst_sck_ao", "i2c_mst_sda_ao" +}; + +static struct meson_pmx_func meson8_functions[] = { + FUNCTION(gpio), + FUNCTION(sd_a), + FUNCTION(sdxc_a), + FUNCTION(pcm_a), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(iso7816), + FUNCTION(i2c_d), + FUNCTION(xtal), + FUNCTION(uart_c), + FUNCTION(pcm_b), + FUNCTION(i2c_c), + FUNCTION(dvin), + FUNCTION(enc), + FUNCTION(vga), + FUNCTION(hdmi), + FUNCTION(spi), + FUNCTION(ethernet), + FUNCTION(i2c_a), + FUNCTION(i2c_b), + FUNCTION(sd_c), + FUNCTION(sdxc_c), + FUNCTION(nand), + FUNCTION(nor), + FUNCTION(sd_b), + FUNCTION(sdxc_b), + FUNCTION(uart_ao), + FUNCTION(remote), + FUNCTION(i2c_slave_ao), + FUNCTION(uart_ao_b), + FUNCTION(i2c_mst_ao), +}; + +static struct meson_bank meson8_banks[] = { + /* name first last pullen pull dir out in */ + BANK("X", PIN_GPIOX_0, PIN_GPIOX_21, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), + BANK("Y", PIN_GPIOY_0, PIN_GPIOY_16, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), + BANK("DV", PIN_GPIODV_0, PIN_GPIODV_29, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), + BANK("H", PIN_GPIOH_0, PIN_GPIOH_9, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), + BANK("Z", PIN_GPIOZ_0, PIN_GPIOZ_14, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17), + BANK("CARD", PIN_CARD_0, PIN_CARD_6, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), + BANK("BOOT", PIN_BOOT_0, PIN_BOOT_18, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), +}; + +static struct meson_bank meson8_ao_banks[] = { + /* name first last pullen pull dir out in */ + BANK("AO", PIN_GPIOAO_0, PIN_GPIO_TEST_N, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), +}; + +static struct meson_domain_data meson8_domain_data[] = { + { + .name = "banks", + .banks = meson8_banks, + .num_banks = ARRAY_SIZE(meson8_banks), + .pin_base = 0, + .num_pins = 120, + }, + { + .name = "ao-bank", + .banks = meson8_ao_banks, + .num_banks = ARRAY_SIZE(meson8_ao_banks), + .pin_base = 120, + .num_pins = 16, + }, +}; + +struct meson_pinctrl_data meson8_pinctrl_data = { + .pins = meson8_pins, + .groups = meson8_groups, + .funcs = meson8_functions, + .domain_data = meson8_domain_data, + .num_pins = ARRAY_SIZE(meson8_pins), + .num_groups = ARRAY_SIZE(meson8_groups), + .num_funcs = ARRAY_SIZE(meson8_functions), + .num_domains = ARRAY_SIZE(meson8_domain_data), +}; diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 224c6cff6aa2..7302f66f4f19 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -145,14 +145,16 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "pcie0", "clkreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)), MPP_MODE(20, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)), MPP_MODE(21, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6810_PLUS), diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c index 89a52e15f0ae..95bfd0653e8f 100644 --- a/drivers/pinctrl/mvebu/pinctrl-dove.c +++ b/drivers/pinctrl/mvebu/pinctrl-dove.c @@ -751,12 +751,12 @@ static struct mvebu_pinctrl_soc_info dove_pinctrl_info = { static struct clk *clk; -static struct of_device_id dove_pinctrl_of_match[] = { +static const struct of_device_id dove_pinctrl_of_match[] = { { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info }, { } }; -static struct regmap_config gc_regmap_config = { +static const struct regmap_config gc_regmap_config = { .reg_bits = 32, .val_bits = 32, .reg_stride = 4, diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index 3d6d97228523..1806b24faa14 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -914,7 +914,7 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev, } } - ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs); + ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &nconfigs); if (nconfigs) { const char *gpio_name; const char *pin; diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index f78b416d7984..4db92f64b4de 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -27,17 +27,6 @@ #include "pinctrl-utils.h" #ifdef CONFIG_DEBUG_FS - -struct pin_config_item { - const enum pin_config_param param; - const char * const display; - const char * const format; - bool has_arg; -}; - -#define PCONFDUMP(a, b, c, d) { .param = a, .display = b, .format = c, \ - .has_arg = d } - static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false), @@ -60,22 +49,25 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true), }; -void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin) +static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, + struct seq_file *s, const char *gname, + unsigned pin, + const struct pin_config_item *items, + int nitems) { - const struct pinconf_ops *ops = pctldev->desc->confops; int i; - if (!ops->is_generic) - return; - - for (i = 0; i < ARRAY_SIZE(conf_items); i++) { + for (i = 0; i < nitems; i++) { unsigned long config; int ret; /* We want to check out this parameter */ - config = pinconf_to_config_packed(conf_items[i].param, 0); - ret = pin_config_get_for_pin(pctldev, pin, &config); + config = pinconf_to_config_packed(items[i].param, 0); + if (gname) + ret = pin_config_group_get(dev_name(pctldev->dev), + gname, &config); + else + ret = pin_config_get_for_pin(pctldev, pin, &config); /* These are legal errors */ if (ret == -EINVAL || ret == -ENOTSUPP) continue; @@ -85,56 +77,47 @@ void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, } /* Space between multiple configs */ seq_puts(s, " "); - seq_puts(s, conf_items[i].display); + seq_puts(s, items[i].display); /* Print unit if available */ - if (conf_items[i].has_arg) { + if (items[i].has_arg) { seq_printf(s, " (%u", pinconf_to_config_argument(config)); - if (conf_items[i].format) - seq_printf(s, " %s)", conf_items[i].format); + if (items[i].format) + seq_printf(s, " %s)", items[i].format); else seq_puts(s, ")"); } } } -void pinconf_generic_dump_group(struct pinctrl_dev *pctldev, - struct seq_file *s, const char *gname) +/** + * pinconf_generic_dump_pins - Print information about pin or group of pins + * @pctldev: Pincontrol device + * @s: File to print to + * @gname: Group name specifying pins + * @pin: Pin number specyfying pin + * + * Print the pinconf configuration for the requested pin(s) to @s. Pins can be + * specified either by pin using @pin or by group using @gname. Only one needs + * to be specified the other can be NULL/0. + */ +void pinconf_generic_dump_pins(struct pinctrl_dev *pctldev, struct seq_file *s, + const char *gname, unsigned pin) { const struct pinconf_ops *ops = pctldev->desc->confops; - int i; if (!ops->is_generic) return; - for (i = 0; i < ARRAY_SIZE(conf_items); i++) { - unsigned long config; - int ret; - - /* We want to check out this parameter */ - config = pinconf_to_config_packed(conf_items[i].param, 0); - ret = pin_config_group_get(dev_name(pctldev->dev), gname, - &config); - /* These are legal errors */ - if (ret == -EINVAL || ret == -ENOTSUPP) - continue; - if (ret) { - seq_printf(s, "ERROR READING CONFIG SETTING %d ", i); - continue; - } - /* Space between multiple configs */ - seq_puts(s, " "); - seq_puts(s, conf_items[i].display); - /* Print unit if available */ - if (conf_items[i].has_arg) { - seq_printf(s, " (%u", - pinconf_to_config_argument(config)); - if (conf_items[i].format) - seq_printf(s, " %s)", conf_items[i].format); - else - seq_puts(s, ")"); - } - } + /* generic parameters */ + pinconf_generic_dump_one(pctldev, s, gname, pin, conf_items, + ARRAY_SIZE(conf_items)); + /* driver-specific parameters */ + if (pctldev->desc->num_custom_params && + pctldev->desc->custom_conf_items) + pinconf_generic_dump_one(pctldev, s, gname, pin, + pctldev->desc->custom_conf_items, + pctldev->desc->num_custom_params); } void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, @@ -148,18 +131,25 @@ void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, seq_printf(s, "%s: 0x%x", conf_items[i].display, pinconf_to_config_argument(config)); } + + if (!pctldev->desc->num_custom_params || + !pctldev->desc->custom_conf_items) + return; + + for (i = 0; i < pctldev->desc->num_custom_params; i++) { + if (pinconf_to_config_param(config) != + pctldev->desc->custom_conf_items[i].param) + continue; + seq_printf(s, "%s: 0x%x", + pctldev->desc->custom_conf_items[i].display, + pinconf_to_config_argument(config)); + } } EXPORT_SYMBOL_GPL(pinconf_generic_dump_config); #endif #ifdef CONFIG_OF -struct pinconf_generic_dt_params { - const char * const property; - enum pin_config_param param; - u32 default_value; -}; - -static const struct pinconf_generic_dt_params dt_params[] = { +static const struct pinconf_generic_params dt_params[] = { { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, @@ -184,6 +174,47 @@ static const struct pinconf_generic_dt_params dt_params[] = { }; /** + * parse_dt_cfg() - Parse DT pinconf parameters + * @np: DT node + * @params: Array of describing generic parameters + * @count: Number of entries in @params + * @cfg: Array of parsed config options + * @ncfg: Number of entries in @cfg + * + * Parse the config options described in @params from @np and puts the result + * in @cfg. @cfg does not need to be empty, entries are added beggining at + * @ncfg. @ncfg is updated to reflect the number of entries after parsing. @cfg + * needs to have enough memory allocated to hold all possible entries. + */ +static void parse_dt_cfg(struct device_node *np, + const struct pinconf_generic_params *params, + unsigned int count, unsigned long *cfg, + unsigned int *ncfg) +{ + int i; + + for (i = 0; i < count; i++) { + u32 val; + int ret; + const struct pinconf_generic_params *par = ¶ms[i]; + + ret = of_property_read_u32(np, par->property, &val); + + /* property not found */ + if (ret == -EINVAL) + continue; + + /* use default value, when no value is specified */ + if (ret) + val = par->default_value; + + pr_debug("found %s with value %u\n", par->property, val); + cfg[*ncfg] = pinconf_to_config_packed(par->param, val); + (*ncfg)++; + } +} + +/** * pinconf_generic_parse_dt_config() * parse the config properties into generic pinconfig values. * @np: node containing the pinconfig properties @@ -191,39 +222,30 @@ static const struct pinconf_generic_dt_params dt_params[] = { * @nconfigs: umber of configurations */ int pinconf_generic_parse_dt_config(struct device_node *np, + struct pinctrl_dev *pctldev, unsigned long **configs, unsigned int *nconfigs) { unsigned long *cfg; - unsigned int ncfg = 0; + unsigned int max_cfg, ncfg = 0; int ret; - int i; - u32 val; if (!np) return -EINVAL; /* allocate a temporary array big enough to hold one of each option */ - cfg = kzalloc(sizeof(*cfg) * ARRAY_SIZE(dt_params), GFP_KERNEL); + max_cfg = ARRAY_SIZE(dt_params); + if (pctldev) + max_cfg += pctldev->desc->num_custom_params; + cfg = kcalloc(max_cfg, sizeof(*cfg), GFP_KERNEL); if (!cfg) return -ENOMEM; - for (i = 0; i < ARRAY_SIZE(dt_params); i++) { - const struct pinconf_generic_dt_params *par = &dt_params[i]; - ret = of_property_read_u32(np, par->property, &val); - - /* property not found */ - if (ret == -EINVAL) - continue; - - /* use default value, when no value is specified */ - if (ret) - val = par->default_value; - - pr_debug("found %s with value %u\n", par->property, val); - cfg[ncfg] = pinconf_to_config_packed(par->param, val); - ncfg++; - } + parse_dt_cfg(np, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg); + if (pctldev && pctldev->desc->num_custom_params && + pctldev->desc->custom_params) + parse_dt_cfg(np, pctldev->desc->custom_params, + pctldev->desc->num_custom_params, cfg, &ncfg); ret = 0; @@ -264,6 +286,7 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, unsigned reserve; struct property *prop; const char *group; + const char *subnode_target_type = "pins"; ret = of_property_read_string(np, "function", &function); if (ret < 0) { @@ -273,7 +296,8 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, function = NULL; } - ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); + ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, + &num_configs); if (ret < 0) { dev_err(dev, "could not parse node property\n"); return ret; @@ -284,10 +308,20 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, reserve++; if (num_configs) reserve++; + ret = of_property_count_strings(np, "pins"); if (ret < 0) { - dev_err(dev, "could not parse property pins\n"); - goto exit; + ret = of_property_count_strings(np, "groups"); + if (ret < 0) { + dev_err(dev, "could not parse property pins/groups\n"); + goto exit; + } + if (type == PIN_MAP_TYPE_INVALID) + type = PIN_MAP_TYPE_CONFIGS_GROUP; + subnode_target_type = "groups"; + } else { + if (type == PIN_MAP_TYPE_INVALID) + type = PIN_MAP_TYPE_CONFIGS_PIN; } reserve *= ret; @@ -296,7 +330,7 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, if (ret < 0) goto exit; - of_property_for_each_string(np, "pins", prop, group) { + of_property_for_each_string(np, subnode_target_type, prop, group) { if (function) { ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, group, diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index 8bfa0643e5dc..1fc09dc20199 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -288,7 +288,7 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev, const struct pinconf_ops *ops = pctldev->desc->confops; /* no-op when not using generic pin config */ - pinconf_generic_dump_pin(pctldev, s, pin); + pinconf_generic_dump_pins(pctldev, s, NULL, pin); if (ops && ops->pin_config_dbg_show) ops->pin_config_dbg_show(pctldev, s, pin); } @@ -333,7 +333,7 @@ static void pinconf_dump_group(struct pinctrl_dev *pctldev, const struct pinconf_ops *ops = pctldev->desc->confops; /* no-op when not using generic pin config */ - pinconf_generic_dump_group(pctldev, s, gname); + pinconf_generic_dump_pins(pctldev, s, gname, 0); if (ops && ops->pin_config_group_dbg_show) ops->pin_config_group_dbg_show(pctldev, s, selector); } diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h index a4a5417e1413..55c75780b3b2 100644 --- a/drivers/pinctrl/pinconf.h +++ b/drivers/pinctrl/pinconf.h @@ -92,26 +92,17 @@ static inline void pinconf_init_device_debugfs(struct dentry *devroot, #if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_DEBUG_FS) -void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin); - -void pinconf_generic_dump_group(struct pinctrl_dev *pctldev, - struct seq_file *s, const char *gname); +void pinconf_generic_dump_pins(struct pinctrl_dev *pctldev, + struct seq_file *s, const char *gname, + unsigned pin); void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned long config); #else -static inline void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, - struct seq_file *s, - unsigned pin) -{ - return; -} - -static inline void pinconf_generic_dump_group(struct pinctrl_dev *pctldev, - struct seq_file *s, - const char *gname) +static inline void pinconf_generic_dump_pins(struct pinctrl_dev *pctldev, + struct seq_file *s, + const char *gname, unsigned pin) { return; } @@ -126,6 +117,7 @@ static inline void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, #if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_OF) int pinconf_generic_parse_dt_config(struct device_node *np, + struct pinctrl_dev *pctldev, unsigned long **configs, unsigned int *nconfigs); #endif diff --git a/drivers/pinctrl/pinctrl-bcm281xx.c b/drivers/pinctrl/pinctrl-bcm281xx.c index fa2a00f22ff1..b88cfe5ed55a 100644 --- a/drivers/pinctrl/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/pinctrl-bcm281xx.c @@ -976,7 +976,7 @@ static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask, *reg_mask |= param_mask; } -static struct regmap_config bcm281xx_pinctrl_regmap_config = { +static const struct regmap_config bcm281xx_pinctrl_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, @@ -1435,7 +1435,7 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) return 0; } -static struct of_device_id bcm281xx_pinctrl_of_match[] = { +static const struct of_device_id bcm281xx_pinctrl_of_match[] = { { .compatible = "brcm,bcm11351-pinctrl", }, { }, }; diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c index 1d21dc226920..0b0fc2eb48e0 100644 --- a/drivers/pinctrl/pinctrl-falcon.c +++ b/drivers/pinctrl/pinctrl-falcon.c @@ -101,6 +101,7 @@ static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len) for (i = 0; i < len; i++) { /* strlen("ioXYZ") + 1 = 6 */ char *name = kzalloc(6, GFP_KERNEL); + snprintf(name, 6, "io%d", base + i); d[i].number = base + i; d[i].name = name; @@ -463,7 +464,7 @@ static int pinctrl_falcon_probe(struct platform_device *pdev) &res); if (IS_ERR(falcon_info.membase[*bank])) return PTR_ERR(falcon_info.membase[*bank]); - + avail = pad_r32(falcon_info.membase[*bank], LTQ_PADC_AVAIL); pins = fls(avail); diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 43eacc924b7e..dee7d5f06c60 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -89,7 +89,7 @@ struct rockchip_iomux { * @reg_pull: optional separate register for additional pull settings * @clk: clock of the gpio bank * @irq: interrupt of the gpio bank - * @saved_enables: Saved content of GPIO_INTEN at suspend time. + * @saved_masks: Saved content of GPIO_INTEN at suspend time. * @pin_base: first pin number * @nr_pins: number of pins in this bank * @name: name of the bank @@ -108,7 +108,7 @@ struct rockchip_pin_bank { struct regmap *regmap_pull; struct clk *clk; int irq; - u32 saved_enables; + u32 saved_masks; u32 pin_base; u8 nr_pins; char *name; @@ -1142,7 +1142,7 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np, return -EINVAL; np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); - ret = pinconf_generic_parse_dt_config(np_config, + ret = pinconf_generic_parse_dt_config(np_config, NULL, &grp->data[j].configs, &grp->data[j].nconfigs); if (ret) return ret; @@ -1545,8 +1545,8 @@ static void rockchip_irq_suspend(struct irq_data *d) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct rockchip_pin_bank *bank = gc->private; - bank->saved_enables = irq_reg_readl(gc, GPIO_INTEN); - irq_reg_writel(gc, gc->wake_active, GPIO_INTEN); + bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); + irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); } static void rockchip_irq_resume(struct irq_data *d) @@ -1554,35 +1554,7 @@ static void rockchip_irq_resume(struct irq_data *d) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct rockchip_pin_bank *bank = gc->private; - irq_reg_writel(gc, bank->saved_enables, GPIO_INTEN); -} - -static void rockchip_irq_disable(struct irq_data *d) -{ - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 val; - - irq_gc_lock(gc); - - val = irq_reg_readl(gc, GPIO_INTEN); - val &= ~d->mask; - irq_reg_writel(gc, val, GPIO_INTEN); - - irq_gc_unlock(gc); -} - -static void rockchip_irq_enable(struct irq_data *d) -{ - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 val; - - irq_gc_lock(gc); - - val = irq_reg_readl(gc, GPIO_INTEN); - val |= d->mask; - irq_reg_writel(gc, val, GPIO_INTEN); - - irq_gc_unlock(gc); + irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); } static int rockchip_interrupts_register(struct platform_device *pdev, @@ -1620,6 +1592,14 @@ static int rockchip_interrupts_register(struct platform_device *pdev, continue; } + /* + * Linux assumes that all interrupts start out disabled/masked. + * Our driver only uses the concept of masked and always keeps + * things enabled, so for us that's all masked and all enabled. + */ + writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); + writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); + gc = irq_get_domain_generic_chip(bank->domain, 0); gc->reg_base = bank->reg_base; gc->private = bank; @@ -1628,8 +1608,6 @@ static int rockchip_interrupts_register(struct platform_device *pdev, gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; - gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; - gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c index 146e48a9b839..fab6aafa6a9f 100644 --- a/drivers/pinctrl/pinctrl-tz1090-pdc.c +++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c @@ -415,7 +415,7 @@ static int tz1090_pdc_pinctrl_dt_subnode_to_map(struct device *dev, function = NULL; } - ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); + ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); if (ret) return ret; diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c index df8cb1e5b7b4..8bd73075f9dd 100644 --- a/drivers/pinctrl/pinctrl-tz1090.c +++ b/drivers/pinctrl/pinctrl-tz1090.c @@ -1131,7 +1131,7 @@ static int tz1090_pinctrl_dt_subnode_to_map(struct device *dev, function = NULL; } - ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); + ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); if (ret) return ret; diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c new file mode 100644 index 000000000000..22280bddb9e2 --- /dev/null +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -0,0 +1,1180 @@ +/* + * Zynq pin controller + * + * Copyright (C) 2014 Xilinx + * + * Sören Brinkmann <soren.brinkmann@xilinx.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#include <linux/io.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/regmap.h> +#include "pinctrl-utils.h" +#include "core.h" + +#define ZYNQ_NUM_MIOS 54 + +#define ZYNQ_PCTRL_MIO_MST_TRI0 0x10c +#define ZYNQ_PCTRL_MIO_MST_TRI1 0x110 + +#define ZYNQ_PINMUX_MUX_SHIFT 1 +#define ZYNQ_PINMUX_MUX_MASK (0x7f << ZYNQ_PINMUX_MUX_SHIFT) + +/** + * struct zynq_pinctrl - driver data + * @pctrl: Pinctrl device + * @syscon: Syscon regmap + * @pctrl_offset: Offset for pinctrl into the @syscon space + * @groups: Pingroups + * @ngroupos: Number of @groups + * @funcs: Pinmux functions + * @nfuncs: Number of @funcs + */ +struct zynq_pinctrl { + struct pinctrl_dev *pctrl; + struct regmap *syscon; + u32 pctrl_offset; + const struct zynq_pctrl_group *groups; + unsigned int ngroups; + const struct zynq_pinmux_function *funcs; + unsigned int nfuncs; +}; + +struct zynq_pctrl_group { + const char *name; + const unsigned int *pins; + const unsigned npins; +}; + +/** + * struct zynq_pinmux_function - a pinmux function + * @name: Name of the pinmux function. + * @groups: List of pingroups for this function. + * @ngroups: Number of entries in @groups. + * @mux_val: Selector for this function + * @mux: Offset of function specific mux + * @mux_mask: Mask for function specific selector + * @mux_shift: Shift for function specific selector + */ +struct zynq_pinmux_function { + const char *name; + const char * const *groups; + unsigned int ngroups; + unsigned int mux_val; + u32 mux; + u32 mux_mask; + u8 mux_shift; +}; + +enum zynq_pinmux_functions { + ZYNQ_PMUX_can0, + ZYNQ_PMUX_can1, + ZYNQ_PMUX_ethernet0, + ZYNQ_PMUX_ethernet1, + ZYNQ_PMUX_gpio0, + ZYNQ_PMUX_i2c0, + ZYNQ_PMUX_i2c1, + ZYNQ_PMUX_mdio0, + ZYNQ_PMUX_mdio1, + ZYNQ_PMUX_qspi0, + ZYNQ_PMUX_qspi1, + ZYNQ_PMUX_qspi_fbclk, + ZYNQ_PMUX_qspi_cs1, + ZYNQ_PMUX_spi0, + ZYNQ_PMUX_spi1, + ZYNQ_PMUX_sdio0, + ZYNQ_PMUX_sdio0_pc, + ZYNQ_PMUX_sdio0_cd, + ZYNQ_PMUX_sdio0_wp, + ZYNQ_PMUX_sdio1, + ZYNQ_PMUX_sdio1_pc, + ZYNQ_PMUX_sdio1_cd, + ZYNQ_PMUX_sdio1_wp, + ZYNQ_PMUX_smc0_nor, + ZYNQ_PMUX_smc0_nor_cs1, + ZYNQ_PMUX_smc0_nor_addr25, + ZYNQ_PMUX_smc0_nand, + ZYNQ_PMUX_ttc0, + ZYNQ_PMUX_ttc1, + ZYNQ_PMUX_uart0, + ZYNQ_PMUX_uart1, + ZYNQ_PMUX_usb0, + ZYNQ_PMUX_usb1, + ZYNQ_PMUX_swdt0, + ZYNQ_PMUX_MAX_FUNC +}; + +const struct pinctrl_pin_desc zynq_pins[] = { + PINCTRL_PIN(0, "MIO0"), + PINCTRL_PIN(1, "MIO1"), + PINCTRL_PIN(2, "MIO2"), + PINCTRL_PIN(3, "MIO3"), + PINCTRL_PIN(4, "MIO4"), + PINCTRL_PIN(5, "MIO5"), + PINCTRL_PIN(6, "MIO6"), + PINCTRL_PIN(7, "MIO7"), + PINCTRL_PIN(8, "MIO8"), + PINCTRL_PIN(9, "MIO9"), + PINCTRL_PIN(10, "MIO10"), + PINCTRL_PIN(11, "MIO11"), + PINCTRL_PIN(12, "MIO12"), + PINCTRL_PIN(13, "MIO13"), + PINCTRL_PIN(14, "MIO14"), + PINCTRL_PIN(15, "MIO15"), + PINCTRL_PIN(16, "MIO16"), + PINCTRL_PIN(17, "MIO17"), + PINCTRL_PIN(18, "MIO18"), + PINCTRL_PIN(19, "MIO19"), + PINCTRL_PIN(20, "MIO20"), + PINCTRL_PIN(21, "MIO21"), + PINCTRL_PIN(22, "MIO22"), + PINCTRL_PIN(23, "MIO23"), + PINCTRL_PIN(24, "MIO24"), + PINCTRL_PIN(25, "MIO25"), + PINCTRL_PIN(26, "MIO26"), + PINCTRL_PIN(27, "MIO27"), + PINCTRL_PIN(28, "MIO28"), + PINCTRL_PIN(29, "MIO29"), + PINCTRL_PIN(30, "MIO30"), + PINCTRL_PIN(31, "MIO31"), + PINCTRL_PIN(32, "MIO32"), + PINCTRL_PIN(33, "MIO33"), + PINCTRL_PIN(34, "MIO34"), + PINCTRL_PIN(35, "MIO35"), + PINCTRL_PIN(36, "MIO36"), + PINCTRL_PIN(37, "MIO37"), + PINCTRL_PIN(38, "MIO38"), + PINCTRL_PIN(39, "MIO39"), + PINCTRL_PIN(40, "MIO40"), + PINCTRL_PIN(41, "MIO41"), + PINCTRL_PIN(42, "MIO42"), + PINCTRL_PIN(43, "MIO43"), + PINCTRL_PIN(44, "MIO44"), + PINCTRL_PIN(45, "MIO45"), + PINCTRL_PIN(46, "MIO46"), + PINCTRL_PIN(47, "MIO47"), + PINCTRL_PIN(48, "MIO48"), + PINCTRL_PIN(49, "MIO49"), + PINCTRL_PIN(50, "MIO50"), + PINCTRL_PIN(51, "MIO51"), + PINCTRL_PIN(52, "MIO52"), + PINCTRL_PIN(53, "MIO53"), + PINCTRL_PIN(54, "EMIO_SD0_WP"), + PINCTRL_PIN(55, "EMIO_SD0_CD"), + PINCTRL_PIN(56, "EMIO_SD1_WP"), + PINCTRL_PIN(57, "EMIO_SD1_CD"), +}; + +/* pin groups */ +static const unsigned int ethernet0_0_pins[] = {16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27}; +static const unsigned int ethernet1_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, + 36, 37, 38, 39}; +static const unsigned int mdio0_0_pins[] = {52, 53}; +static const unsigned int mdio1_0_pins[] = {52, 53}; +static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6}; + +static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13}; +static const unsigned int qspi_cs1_pins[] = {0}; +static const unsigned int qspi_fbclk_pins[] = {8}; +static const unsigned int spi0_0_pins[] = {16, 17, 18, 19, 20, 21}; +static const unsigned int spi0_1_pins[] = {28, 29, 30, 31, 32, 33}; +static const unsigned int spi0_2_pins[] = {40, 41, 42, 43, 44, 45}; +static const unsigned int spi1_0_pins[] = {10, 11, 12, 13, 14, 15}; +static const unsigned int spi1_1_pins[] = {22, 23, 24, 25, 26, 27}; +static const unsigned int spi1_2_pins[] = {34, 35, 36, 37, 38, 39}; +static const unsigned int spi1_3_pins[] = {46, 47, 48, 49, 40, 51}; +static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21}; +static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33}; +static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45}; +static const unsigned int sdio1_0_pins[] = {10, 11, 12, 13, 14, 15}; +static const unsigned int sdio1_1_pins[] = {22, 23, 24, 25, 26, 27}; +static const unsigned int sdio1_2_pins[] = {34, 35, 36, 37, 38, 39}; +static const unsigned int sdio1_3_pins[] = {46, 47, 48, 49, 40, 51}; +static const unsigned int sdio0_emio_wp_pins[] = {54}; +static const unsigned int sdio0_emio_cd_pins[] = {55}; +static const unsigned int sdio1_emio_wp_pins[] = {56}; +static const unsigned int sdio1_emio_cd_pins[] = {57}; +static const unsigned int smc0_nor_pins[] = {0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, + 15, 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, 32, + 33, 34, 35, 36, 37, 38, 39}; +static const unsigned int smc0_nor_cs1_pins[] = {1}; +static const unsigned int smc0_nor_addr25_pins[] = {1}; +static const unsigned int smc0_nand_pins[] = {0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 16, 17, 18, 19, 20, + 21, 22, 23}; +/* Note: CAN MIO clock inputs are modeled in the clock framework */ +static const unsigned int can0_0_pins[] = {10, 11}; +static const unsigned int can0_1_pins[] = {14, 15}; +static const unsigned int can0_2_pins[] = {18, 19}; +static const unsigned int can0_3_pins[] = {22, 23}; +static const unsigned int can0_4_pins[] = {26, 27}; +static const unsigned int can0_5_pins[] = {30, 31}; +static const unsigned int can0_6_pins[] = {34, 35}; +static const unsigned int can0_7_pins[] = {38, 39}; +static const unsigned int can0_8_pins[] = {42, 43}; +static const unsigned int can0_9_pins[] = {46, 47}; +static const unsigned int can0_10_pins[] = {50, 51}; +static const unsigned int can1_0_pins[] = {8, 9}; +static const unsigned int can1_1_pins[] = {12, 13}; +static const unsigned int can1_2_pins[] = {16, 17}; +static const unsigned int can1_3_pins[] = {20, 21}; +static const unsigned int can1_4_pins[] = {24, 25}; +static const unsigned int can1_5_pins[] = {28, 29}; +static const unsigned int can1_6_pins[] = {32, 33}; +static const unsigned int can1_7_pins[] = {36, 37}; +static const unsigned int can1_8_pins[] = {40, 41}; +static const unsigned int can1_9_pins[] = {44, 45}; +static const unsigned int can1_10_pins[] = {48, 49}; +static const unsigned int can1_11_pins[] = {52, 53}; +static const unsigned int uart0_0_pins[] = {10, 11}; +static const unsigned int uart0_1_pins[] = {14, 15}; +static const unsigned int uart0_2_pins[] = {18, 19}; +static const unsigned int uart0_3_pins[] = {22, 23}; +static const unsigned int uart0_4_pins[] = {26, 27}; +static const unsigned int uart0_5_pins[] = {30, 31}; +static const unsigned int uart0_6_pins[] = {34, 35}; +static const unsigned int uart0_7_pins[] = {38, 39}; +static const unsigned int uart0_8_pins[] = {42, 43}; +static const unsigned int uart0_9_pins[] = {46, 47}; +static const unsigned int uart0_10_pins[] = {50, 51}; +static const unsigned int uart1_0_pins[] = {8, 9}; +static const unsigned int uart1_1_pins[] = {12, 13}; +static const unsigned int uart1_2_pins[] = {16, 17}; +static const unsigned int uart1_3_pins[] = {20, 21}; +static const unsigned int uart1_4_pins[] = {24, 25}; +static const unsigned int uart1_5_pins[] = {28, 29}; +static const unsigned int uart1_6_pins[] = {32, 33}; +static const unsigned int uart1_7_pins[] = {36, 37}; +static const unsigned int uart1_8_pins[] = {40, 41}; +static const unsigned int uart1_9_pins[] = {44, 45}; +static const unsigned int uart1_10_pins[] = {48, 49}; +static const unsigned int uart1_11_pins[] = {52, 53}; +static const unsigned int i2c0_0_pins[] = {10, 11}; +static const unsigned int i2c0_1_pins[] = {14, 15}; +static const unsigned int i2c0_2_pins[] = {18, 19}; +static const unsigned int i2c0_3_pins[] = {22, 23}; +static const unsigned int i2c0_4_pins[] = {26, 27}; +static const unsigned int i2c0_5_pins[] = {30, 31}; +static const unsigned int i2c0_6_pins[] = {34, 35}; +static const unsigned int i2c0_7_pins[] = {38, 39}; +static const unsigned int i2c0_8_pins[] = {42, 43}; +static const unsigned int i2c0_9_pins[] = {46, 47}; +static const unsigned int i2c0_10_pins[] = {50, 51}; +static const unsigned int i2c1_0_pins[] = {12, 13}; +static const unsigned int i2c1_1_pins[] = {16, 17}; +static const unsigned int i2c1_2_pins[] = {20, 21}; +static const unsigned int i2c1_3_pins[] = {24, 25}; +static const unsigned int i2c1_4_pins[] = {28, 29}; +static const unsigned int i2c1_5_pins[] = {32, 33}; +static const unsigned int i2c1_6_pins[] = {36, 37}; +static const unsigned int i2c1_7_pins[] = {40, 41}; +static const unsigned int i2c1_8_pins[] = {44, 45}; +static const unsigned int i2c1_9_pins[] = {48, 49}; +static const unsigned int i2c1_10_pins[] = {52, 53}; +static const unsigned int ttc0_0_pins[] = {18, 19}; +static const unsigned int ttc0_1_pins[] = {30, 31}; +static const unsigned int ttc0_2_pins[] = {42, 43}; +static const unsigned int ttc1_0_pins[] = {16, 17}; +static const unsigned int ttc1_1_pins[] = {28, 29}; +static const unsigned int ttc1_2_pins[] = {40, 41}; +static const unsigned int swdt0_0_pins[] = {14, 15}; +static const unsigned int swdt0_1_pins[] = {26, 27}; +static const unsigned int swdt0_2_pins[] = {38, 39}; +static const unsigned int swdt0_3_pins[] = {50, 51}; +static const unsigned int swdt0_4_pins[] = {52, 53}; +static const unsigned int gpio0_0_pins[] = {0}; +static const unsigned int gpio0_1_pins[] = {1}; +static const unsigned int gpio0_2_pins[] = {2}; +static const unsigned int gpio0_3_pins[] = {3}; +static const unsigned int gpio0_4_pins[] = {4}; +static const unsigned int gpio0_5_pins[] = {5}; +static const unsigned int gpio0_6_pins[] = {6}; +static const unsigned int gpio0_7_pins[] = {7}; +static const unsigned int gpio0_8_pins[] = {8}; +static const unsigned int gpio0_9_pins[] = {9}; +static const unsigned int gpio0_10_pins[] = {10}; +static const unsigned int gpio0_11_pins[] = {11}; +static const unsigned int gpio0_12_pins[] = {12}; +static const unsigned int gpio0_13_pins[] = {13}; +static const unsigned int gpio0_14_pins[] = {14}; +static const unsigned int gpio0_15_pins[] = {15}; +static const unsigned int gpio0_16_pins[] = {16}; +static const unsigned int gpio0_17_pins[] = {17}; +static const unsigned int gpio0_18_pins[] = {18}; +static const unsigned int gpio0_19_pins[] = {19}; +static const unsigned int gpio0_20_pins[] = {20}; +static const unsigned int gpio0_21_pins[] = {21}; +static const unsigned int gpio0_22_pins[] = {22}; +static const unsigned int gpio0_23_pins[] = {23}; +static const unsigned int gpio0_24_pins[] = {24}; +static const unsigned int gpio0_25_pins[] = {25}; +static const unsigned int gpio0_26_pins[] = {26}; +static const unsigned int gpio0_27_pins[] = {27}; +static const unsigned int gpio0_28_pins[] = {28}; +static const unsigned int gpio0_29_pins[] = {29}; +static const unsigned int gpio0_30_pins[] = {30}; +static const unsigned int gpio0_31_pins[] = {31}; +static const unsigned int gpio0_32_pins[] = {32}; +static const unsigned int gpio0_33_pins[] = {33}; +static const unsigned int gpio0_34_pins[] = {34}; +static const unsigned int gpio0_35_pins[] = {35}; +static const unsigned int gpio0_36_pins[] = {36}; +static const unsigned int gpio0_37_pins[] = {37}; +static const unsigned int gpio0_38_pins[] = {38}; +static const unsigned int gpio0_39_pins[] = {39}; +static const unsigned int gpio0_40_pins[] = {40}; +static const unsigned int gpio0_41_pins[] = {41}; +static const unsigned int gpio0_42_pins[] = {42}; +static const unsigned int gpio0_43_pins[] = {43}; +static const unsigned int gpio0_44_pins[] = {44}; +static const unsigned int gpio0_45_pins[] = {45}; +static const unsigned int gpio0_46_pins[] = {46}; +static const unsigned int gpio0_47_pins[] = {47}; +static const unsigned int gpio0_48_pins[] = {48}; +static const unsigned int gpio0_49_pins[] = {49}; +static const unsigned int gpio0_50_pins[] = {50}; +static const unsigned int gpio0_51_pins[] = {51}; +static const unsigned int gpio0_52_pins[] = {52}; +static const unsigned int gpio0_53_pins[] = {53}; +static const unsigned int usb0_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, 36, + 37, 38, 39}; +static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, + 49, 50, 51}; + +#define DEFINE_ZYNQ_PINCTRL_GRP(nm) \ + { \ + .name = #nm "_grp", \ + .pins = nm ## _pins, \ + .npins = ARRAY_SIZE(nm ## _pins), \ + } + +struct zynq_pctrl_group zynq_pctrl_groups[] = { + DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0), + DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0), + DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0), + DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0), + DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0), + DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0), + DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk), + DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3), + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0), + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1), + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2), + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0), + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1), + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2), + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3), + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp), + DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd), + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp), + DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd), + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor), + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1), + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25), + DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand), + DEFINE_ZYNQ_PINCTRL_GRP(can0_0), + DEFINE_ZYNQ_PINCTRL_GRP(can0_1), + DEFINE_ZYNQ_PINCTRL_GRP(can0_2), + DEFINE_ZYNQ_PINCTRL_GRP(can0_3), + DEFINE_ZYNQ_PINCTRL_GRP(can0_4), + DEFINE_ZYNQ_PINCTRL_GRP(can0_5), + DEFINE_ZYNQ_PINCTRL_GRP(can0_6), + DEFINE_ZYNQ_PINCTRL_GRP(can0_7), + DEFINE_ZYNQ_PINCTRL_GRP(can0_8), + DEFINE_ZYNQ_PINCTRL_GRP(can0_9), + DEFINE_ZYNQ_PINCTRL_GRP(can0_10), + DEFINE_ZYNQ_PINCTRL_GRP(can1_0), + DEFINE_ZYNQ_PINCTRL_GRP(can1_1), + DEFINE_ZYNQ_PINCTRL_GRP(can1_2), + DEFINE_ZYNQ_PINCTRL_GRP(can1_3), + DEFINE_ZYNQ_PINCTRL_GRP(can1_4), + DEFINE_ZYNQ_PINCTRL_GRP(can1_5), + DEFINE_ZYNQ_PINCTRL_GRP(can1_6), + DEFINE_ZYNQ_PINCTRL_GRP(can1_7), + DEFINE_ZYNQ_PINCTRL_GRP(can1_8), + DEFINE_ZYNQ_PINCTRL_GRP(can1_9), + DEFINE_ZYNQ_PINCTRL_GRP(can1_10), + DEFINE_ZYNQ_PINCTRL_GRP(can1_11), + DEFINE_ZYNQ_PINCTRL_GRP(uart0_0), + DEFINE_ZYNQ_PINCTRL_GRP(uart0_1), + DEFINE_ZYNQ_PINCTRL_GRP(uart0_2), + DEFINE_ZYNQ_PINCTRL_GRP(uart0_3), + DEFINE_ZYNQ_PINCTRL_GRP(uart0_4), + DEFINE_ZYNQ_PINCTRL_GRP(uart0_5), + DEFINE_ZYNQ_PINCTRL_GRP(uart0_6), + DEFINE_ZYNQ_PINCTRL_GRP(uart0_7), + DEFINE_ZYNQ_PINCTRL_GRP(uart0_8), + DEFINE_ZYNQ_PINCTRL_GRP(uart0_9), + DEFINE_ZYNQ_PINCTRL_GRP(uart0_10), + DEFINE_ZYNQ_PINCTRL_GRP(uart1_0), + DEFINE_ZYNQ_PINCTRL_GRP(uart1_1), + DEFINE_ZYNQ_PINCTRL_GRP(uart1_2), + DEFINE_ZYNQ_PINCTRL_GRP(uart1_3), + DEFINE_ZYNQ_PINCTRL_GRP(uart1_4), + DEFINE_ZYNQ_PINCTRL_GRP(uart1_5), + DEFINE_ZYNQ_PINCTRL_GRP(uart1_6), + DEFINE_ZYNQ_PINCTRL_GRP(uart1_7), + DEFINE_ZYNQ_PINCTRL_GRP(uart1_8), + DEFINE_ZYNQ_PINCTRL_GRP(uart1_9), + DEFINE_ZYNQ_PINCTRL_GRP(uart1_10), + DEFINE_ZYNQ_PINCTRL_GRP(uart1_11), + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0), + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1), + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2), + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3), + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4), + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5), + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6), + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7), + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8), + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9), + DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10), + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0), + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1), + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2), + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3), + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4), + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5), + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6), + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7), + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8), + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9), + DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10), + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0), + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1), + DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2), + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0), + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1), + DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2), + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0), + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1), + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2), + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3), + DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_0), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_1), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_2), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_3), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_4), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_5), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_6), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_7), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_8), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_9), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_10), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_11), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_12), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_13), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_14), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_15), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_16), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_17), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_18), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_19), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_20), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_21), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_22), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_23), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_24), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_25), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_26), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_27), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_28), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_29), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_30), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_31), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_32), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_33), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_34), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_35), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_36), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_37), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_38), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_39), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_40), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_41), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_42), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_43), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_44), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_45), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_46), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_47), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_48), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_49), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_50), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_51), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_52), + DEFINE_ZYNQ_PINCTRL_GRP(gpio0_53), + DEFINE_ZYNQ_PINCTRL_GRP(usb0_0), + DEFINE_ZYNQ_PINCTRL_GRP(usb1_0), +}; + +/* function groups */ +static const char * const ethernet0_groups[] = {"ethernet0_0_grp"}; +static const char * const ethernet1_groups[] = {"ethernet1_0_grp"}; +static const char * const usb0_groups[] = {"usb0_0_grp"}; +static const char * const usb1_groups[] = {"usb1_0_grp"}; +static const char * const mdio0_groups[] = {"mdio0_0_grp"}; +static const char * const mdio1_groups[] = {"mdio1_0_grp"}; +static const char * const qspi0_groups[] = {"qspi0_0_grp"}; +static const char * const qspi1_groups[] = {"qspi0_1_grp"}; +static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"}; +static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"}; +static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp", + "spi0_2_grp"}; +static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp", + "spi1_2_grp", "spi1_3_grp"}; +static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp", + "sdio0_2_grp"}; +static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp", + "sdio1_2_grp", "sdio1_3_grp"}; +static const char * const sdio0_pc_groups[] = {"gpio0_0_grp", + "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", + "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp", + "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", + "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", + "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", + "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", + "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", + "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", + "gpio0_50_grp", "gpio0_52_grp"}; +static const char * const sdio1_pc_groups[] = {"gpio0_1_grp", + "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp", + "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", + "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", + "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", + "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", + "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", + "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", + "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", + "gpio0_51_grp", "gpio0_53_grp"}; +static const char * const sdio0_cd_groups[] = {"gpio0_0_grp", + "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", + "gpio0_10_grp", "gpio0_12_grp", + "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", + "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", + "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", + "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", + "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", + "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", + "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", + "gpio0_3_grp", "gpio0_5_grp", + "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", + "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", + "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", + "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", + "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", + "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", + "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", + "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_cd_grp"}; +static const char * const sdio0_wp_groups[] = {"gpio0_0_grp", + "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", + "gpio0_10_grp", "gpio0_12_grp", + "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", + "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", + "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", + "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", + "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", + "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", + "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", + "gpio0_3_grp", "gpio0_5_grp", + "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", + "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", + "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", + "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", + "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", + "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", + "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", + "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_wp_grp"}; +static const char * const sdio1_cd_groups[] = {"gpio0_0_grp", + "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", + "gpio0_10_grp", "gpio0_12_grp", + "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", + "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", + "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", + "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", + "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", + "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", + "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", + "gpio0_3_grp", "gpio0_5_grp", + "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", + "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", + "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", + "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", + "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", + "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", + "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", + "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_cd_grp"}; +static const char * const sdio1_wp_groups[] = {"gpio0_0_grp", + "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", + "gpio0_10_grp", "gpio0_12_grp", + "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", + "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", + "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", + "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", + "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", + "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", + "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", + "gpio0_3_grp", "gpio0_5_grp", + "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", + "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", + "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", + "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", + "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", + "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", + "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", + "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"}; +static const char * const smc0_nor_groups[] = {"smc0_nor"}; +static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"}; +static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"}; +static const char * const smc0_nand_groups[] = {"smc0_nand"}; +static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp", + "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp", + "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp", + "can0_10_grp"}; +static const char * const can1_groups[] = {"can1_0_grp", "can1_1_grp", + "can1_2_grp", "can1_3_grp", "can1_4_grp", "can1_5_grp", + "can1_6_grp", "can1_7_grp", "can1_8_grp", "can1_9_grp", + "can1_10_grp", "can1_11_grp"}; +static const char * const uart0_groups[] = {"uart0_0_grp", "uart0_1_grp", + "uart0_2_grp", "uart0_3_grp", "uart0_4_grp", "uart0_5_grp", + "uart0_6_grp", "uart0_7_grp", "uart0_8_grp", "uart0_9_grp", + "uart0_10_grp"}; +static const char * const uart1_groups[] = {"uart1_0_grp", "uart1_1_grp", + "uart1_2_grp", "uart1_3_grp", "uart1_4_grp", "uart1_5_grp", + "uart1_6_grp", "uart1_7_grp", "uart1_8_grp", "uart1_9_grp", + "uart1_10_grp", "uart1_11_grp"}; +static const char * const i2c0_groups[] = {"i2c0_0_grp", "i2c0_1_grp", + "i2c0_2_grp", "i2c0_3_grp", "i2c0_4_grp", "i2c0_5_grp", + "i2c0_6_grp", "i2c0_7_grp", "i2c0_8_grp", "i2c0_9_grp", + "i2c0_10_grp"}; +static const char * const i2c1_groups[] = {"i2c1_0_grp", "i2c1_1_grp", + "i2c1_2_grp", "i2c1_3_grp", "i2c1_4_grp", "i2c1_5_grp", + "i2c1_6_grp", "i2c1_7_grp", "i2c1_8_grp", "i2c1_9_grp", + "i2c1_10_grp"}; +static const char * const ttc0_groups[] = {"ttc0_0_grp", "ttc0_1_grp", + "ttc0_2_grp"}; +static const char * const ttc1_groups[] = {"ttc1_0_grp", "ttc1_1_grp", + "ttc1_2_grp"}; +static const char * const swdt0_groups[] = {"swdt0_0_grp", "swdt0_1_grp", + "swdt0_2_grp", "swdt0_3_grp", "swdt0_4_grp"}; +static const char * const gpio0_groups[] = {"gpio0_0_grp", + "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", + "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp", + "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", + "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", + "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", + "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", + "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", + "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", + "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", + "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp", + "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", + "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", + "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", + "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", + "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", + "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", + "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", + "gpio0_51_grp", "gpio0_53_grp"}; + +#define DEFINE_ZYNQ_PINMUX_FUNCTION(fname, mval) \ + [ZYNQ_PMUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + .mux_val = mval, \ + } + +#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, mux, mask, shift) \ + [ZYNQ_PMUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + .mux_val = mval, \ + .mux_mask = mask, \ + .mux_shift = shift, \ + } + +#define ZYNQ_SDIO_WP_SHIFT 0 +#define ZYNQ_SDIO_WP_MASK (0x3f << ZYNQ_SDIO_WP_SHIFT) +#define ZYNQ_SDIO_CD_SHIFT 16 +#define ZYNQ_SDIO_CD_MASK (0x3f << ZYNQ_SDIO_CD_SHIFT) + +static const struct zynq_pinmux_function zynq_pmux_functions[] = { + DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet0, 1), + DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet1, 1), + DEFINE_ZYNQ_PINMUX_FUNCTION(usb0, 2), + DEFINE_ZYNQ_PINMUX_FUNCTION(usb1, 2), + DEFINE_ZYNQ_PINMUX_FUNCTION(mdio0, 0x40), + DEFINE_ZYNQ_PINMUX_FUNCTION(mdio1, 0x50), + DEFINE_ZYNQ_PINMUX_FUNCTION(qspi0, 1), + DEFINE_ZYNQ_PINMUX_FUNCTION(qspi1, 1), + DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_fbclk, 1), + DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1), + DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50), + DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50), + DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40), + DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc), + DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 130, ZYNQ_SDIO_WP_MASK, + ZYNQ_SDIO_WP_SHIFT), + DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 130, ZYNQ_SDIO_CD_MASK, + ZYNQ_SDIO_CD_SHIFT), + DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40), + DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc), + DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 134, ZYNQ_SDIO_WP_MASK, + ZYNQ_SDIO_WP_SHIFT), + DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 134, ZYNQ_SDIO_CD_MASK, + ZYNQ_SDIO_CD_SHIFT), + DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4), + DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8), + DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_addr25, 4), + DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nand, 8), + DEFINE_ZYNQ_PINMUX_FUNCTION(can0, 0x10), + DEFINE_ZYNQ_PINMUX_FUNCTION(can1, 0x10), + DEFINE_ZYNQ_PINMUX_FUNCTION(uart0, 0x70), + DEFINE_ZYNQ_PINMUX_FUNCTION(uart1, 0x70), + DEFINE_ZYNQ_PINMUX_FUNCTION(i2c0, 0x20), + DEFINE_ZYNQ_PINMUX_FUNCTION(i2c1, 0x20), + DEFINE_ZYNQ_PINMUX_FUNCTION(ttc0, 0x60), + DEFINE_ZYNQ_PINMUX_FUNCTION(ttc1, 0x60), + DEFINE_ZYNQ_PINMUX_FUNCTION(swdt0, 0x30), + DEFINE_ZYNQ_PINMUX_FUNCTION(gpio0, 0), +}; + + +/* pinctrl */ +static int zynq_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->ngroups; +} + +static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->groups[selector].name; +} + +static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned selector, + const unsigned **pins, + unsigned *num_pins) +{ + struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = pctrl->groups[selector].pins; + *num_pins = pctrl->groups[selector].npins; + + return 0; +} + +static const struct pinctrl_ops zynq_pctrl_ops = { + .get_groups_count = zynq_pctrl_get_groups_count, + .get_group_name = zynq_pctrl_get_group_name, + .get_group_pins = zynq_pctrl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +/* pinmux */ +static int zynq_pmux_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->nfuncs; +} + +static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->funcs[selector].name; +} + +static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev, + unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctrl->funcs[selector].groups; + *num_groups = pctrl->funcs[selector].ngroups; + return 0; +} + +static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + int i, ret; + struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct zynq_pctrl_group *pgrp = &pctrl->groups[group]; + const struct zynq_pinmux_function *func = &pctrl->funcs[function]; + + /* + * SD WP & CD are special. They have dedicated registers + * to mux them in + */ + if (function == ZYNQ_PMUX_sdio0_cd || function == ZYNQ_PMUX_sdio0_wp || + function == ZYNQ_PMUX_sdio1_cd || + function == ZYNQ_PMUX_sdio1_wp) { + u32 reg; + + ret = regmap_read(pctrl->syscon, + pctrl->pctrl_offset + func->mux, ®); + if (ret) + return ret; + + reg &= ~func->mux_mask; + reg |= pgrp->pins[0] << func->mux_shift; + ret = regmap_write(pctrl->syscon, + pctrl->pctrl_offset + func->mux, reg); + if (ret) + return ret; + } else { + for (i = 0; i < pgrp->npins; i++) { + unsigned int pin = pgrp->pins[i]; + u32 reg, addr = pctrl->pctrl_offset + (4 * pin); + + ret = regmap_read(pctrl->syscon, addr, ®); + if (ret) + return ret; + + reg &= ~ZYNQ_PINMUX_MUX_MASK; + reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT; + ret = regmap_write(pctrl->syscon, addr, reg); + if (ret) + return ret; + } + } + + return 0; +} + +static const struct pinmux_ops zynq_pinmux_ops = { + .get_functions_count = zynq_pmux_get_functions_count, + .get_function_name = zynq_pmux_get_function_name, + .get_function_groups = zynq_pmux_get_function_groups, + .set_mux = zynq_pinmux_set_mux, +}; + +/* pinconfig */ +#define ZYNQ_PINCONF_TRISTATE BIT(0) +#define ZYNQ_PINCONF_SPEED BIT(8) +#define ZYNQ_PINCONF_PULLUP BIT(12) +#define ZYNQ_PINCONF_DISABLE_RECVR BIT(13) + +#define ZYNQ_PINCONF_IOTYPE_SHIFT 9 +#define ZYNQ_PINCONF_IOTYPE_MASK (7 << ZYNQ_PINCONF_IOTYPE_SHIFT) + +enum zynq_io_standards { + zynq_iostd_min, + zynq_iostd_lvcmos18, + zynq_iostd_lvcmos25, + zynq_iostd_lvcmos33, + zynq_iostd_hstl, + zynq_iostd_max +}; + +/** + * enum zynq_pin_config_param - possible pin configuration parameters + * @PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to + * this parameter (on a custom format) tells the driver which alternative + * IO standard to use. + */ +enum zynq_pin_config_param { + PIN_CONFIG_IOSTANDARD = PIN_CONFIG_END + 1, +}; + +static const struct pinconf_generic_params zynq_dt_params[] = { + {"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18}, +}; + +#ifdef CONFIG_DEBUG_FS +static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)] = { + PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true), +}; +#endif + +static unsigned int zynq_pinconf_iostd_get(u32 reg) +{ + return (reg & ZYNQ_PINCONF_IOTYPE_MASK) >> ZYNQ_PINCONF_IOTYPE_SHIFT; +} + +static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *config) +{ + u32 reg; + int ret; + unsigned int arg = 0; + unsigned int param = pinconf_to_config_param(*config); + struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + if (pin >= ZYNQ_NUM_MIOS) + return -ENOTSUPP; + + ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®); + if (ret) + return -EIO; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + if (!(reg & ZYNQ_PINCONF_PULLUP)) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + if (!(reg & ZYNQ_PINCONF_TRISTATE)) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_DISABLE: + if (reg & ZYNQ_PINCONF_PULLUP || reg & ZYNQ_PINCONF_TRISTATE) + return -EINVAL; + break; + case PIN_CONFIG_SLEW_RATE: + arg = !!(reg & ZYNQ_PINCONF_SPEED); + break; + case PIN_CONFIG_LOW_POWER_MODE: + { + enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg); + + if (iostd != zynq_iostd_hstl) + return -EINVAL; + if (!(reg & ZYNQ_PINCONF_DISABLE_RECVR)) + return -EINVAL; + arg = !!(reg & ZYNQ_PINCONF_DISABLE_RECVR); + break; + } + case PIN_CONFIG_IOSTANDARD: + arg = zynq_pinconf_iostd_get(reg); + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs) +{ + int i, ret; + u32 reg; + u32 pullup = 0; + u32 tristate = 0; + struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + if (pin >= ZYNQ_NUM_MIOS) + return -ENOTSUPP; + + ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®); + if (ret) + return -EIO; + + for (i = 0; i < num_configs; i++) { + unsigned int param = pinconf_to_config_param(configs[i]); + unsigned int arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + pullup = ZYNQ_PINCONF_PULLUP; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + tristate = ZYNQ_PINCONF_TRISTATE; + break; + case PIN_CONFIG_BIAS_DISABLE: + reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE); + break; + case PIN_CONFIG_SLEW_RATE: + if (arg) + reg |= ZYNQ_PINCONF_SPEED; + else + reg &= ~ZYNQ_PINCONF_SPEED; + + break; + case PIN_CONFIG_IOSTANDARD: + if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) { + dev_warn(pctldev->dev, + "unsupported IO standard '%u'\n", + param); + break; + } + reg &= ~ZYNQ_PINCONF_IOTYPE_MASK; + reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT; + break; + case PIN_CONFIG_LOW_POWER_MODE: + if (arg) + reg |= ZYNQ_PINCONF_DISABLE_RECVR; + else + reg &= ~ZYNQ_PINCONF_DISABLE_RECVR; + + break; + default: + dev_warn(pctldev->dev, + "unsupported configuration parameter '%u'\n", + param); + continue; + } + } + + if (tristate || pullup) { + reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE); + reg |= tristate | pullup; + } + + ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg); + if (ret) + return -EIO; + + return 0; +} + +static int zynq_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned selector, + unsigned long *configs, + unsigned num_configs) +{ + int i, ret; + struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct zynq_pctrl_group *pgrp = &pctrl->groups[selector]; + + for (i = 0; i < pgrp->npins; i++) { + ret = zynq_pinconf_cfg_set(pctldev, pgrp->pins[i], configs, + num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops zynq_pinconf_ops = { + .is_generic = true, + .pin_config_get = zynq_pinconf_cfg_get, + .pin_config_set = zynq_pinconf_cfg_set, + .pin_config_group_set = zynq_pinconf_group_set, +}; + +static struct pinctrl_desc zynq_desc = { + .name = "zynq_pinctrl", + .pins = zynq_pins, + .npins = ARRAY_SIZE(zynq_pins), + .pctlops = &zynq_pctrl_ops, + .pmxops = &zynq_pinmux_ops, + .confops = &zynq_pinconf_ops, + .num_custom_params = ARRAY_SIZE(zynq_dt_params), + .custom_params = zynq_dt_params, +#ifdef CONFIG_DEBUG_FS + .custom_conf_items = zynq_conf_items, +#endif + .owner = THIS_MODULE, +}; + +static int zynq_pinctrl_probe(struct platform_device *pdev) + +{ + struct resource *res; + struct zynq_pinctrl *pctrl; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "syscon"); + if (IS_ERR(pctrl->syscon)) { + dev_err(&pdev->dev, "unable to get syscon\n"); + return PTR_ERR(pctrl->syscon); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "missing IO resource\n"); + return -ENODEV; + } + pctrl->pctrl_offset = res->start; + + pctrl->groups = zynq_pctrl_groups; + pctrl->ngroups = ARRAY_SIZE(zynq_pctrl_groups); + pctrl->funcs = zynq_pmux_functions; + pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions); + + pctrl->pctrl = pinctrl_register(&zynq_desc, &pdev->dev, pctrl); + if (!pctrl->pctrl) + return -ENOMEM; + + platform_set_drvdata(pdev, pctrl); + + dev_info(&pdev->dev, "zynq pinctrl initialized\n"); + + return 0; +} + +int zynq_pinctrl_remove(struct platform_device *pdev) +{ + struct zynq_pinctrl *pctrl = platform_get_drvdata(pdev); + + pinctrl_unregister(pctrl->pctrl); + + return 0; +} + +static const struct of_device_id zynq_pinctrl_of_match[] = { + { .compatible = "xlnx,pinctrl-zynq" }, + { } +}; +MODULE_DEVICE_TABLE(of, zynq_pinctrl_of_match); + +static struct platform_driver zynq_pinctrl_driver = { + .driver = { + .name = "zynq-pinctrl", + .of_match_table = zynq_pinctrl_of_match, + }, + .probe = zynq_pinctrl_probe, + .remove = zynq_pinctrl_remove, +}; + +module_platform_driver(zynq_pinctrl_driver); + +MODULE_AUTHOR("Sören Brinkmann <soren.brinkmann@xilinx.com>"); +MODULE_DESCRIPTION("Xilinx Zynq pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 3cd243c26b7d..ea575f60f001 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -47,6 +47,14 @@ config PINCTRL_MSM8X74 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8974 platform. +config PINCTRL_MSM8916 + tristate "Qualcomm 8916 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found on the Qualcomm 8916 platform. + config PINCTRL_QCOM_SPMI_PMIC tristate "Qualcomm SPMI PMIC pin controller driver" depends on GPIOLIB && OF && SPMI diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index bfd79af5f982..68958702917d 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -5,5 +5,6 @@ obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o +obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index ed7017df065d..a535f9c23678 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -204,21 +204,6 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, return 0; } -static int msm_config_get(struct pinctrl_dev *pctldev, - unsigned int pin, - unsigned long *config) -{ - dev_err(pctldev->dev, "pin_config_set op not supported\n"); - return -ENOTSUPP; -} - -static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *configs, unsigned num_configs) -{ - dev_err(pctldev->dev, "pin_config_set op not supported\n"); - return -ENOTSUPP; -} - #define MSM_NO_PULL 0 #define MSM_PULL_DOWN 1 #define MSM_KEEPER 2 @@ -372,8 +357,6 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, } static const struct pinconf_ops msm_pinconf_ops = { - .pin_config_get = msm_config_get, - .pin_config_set = msm_config_set, .pin_config_group_get = msm_config_group_get, .pin_config_group_set = msm_config_group_set, }; diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index b952c4b4a8e9..54fdd04ce9d5 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -70,11 +70,11 @@ struct msm_pingroup { unsigned *funcs; unsigned nfuncs; - s16 ctl_reg; - s16 io_reg; - s16 intr_cfg_reg; - s16 intr_status_reg; - s16 intr_target_reg; + u32 ctl_reg; + u32 io_reg; + u32 intr_cfg_reg; + u32 intr_status_reg; + u32 intr_target_reg; unsigned mux_bit:5; diff --git a/drivers/pinctrl/qcom/pinctrl-msm8916.c b/drivers/pinctrl/qcom/pinctrl-msm8916.c new file mode 100644 index 000000000000..20ebf244e80d --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c @@ -0,0 +1,1005 @@ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8916_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "SDC1_CLK"), + PINCTRL_PIN(123, "SDC1_CMD"), + PINCTRL_PIN(124, "SDC1_DATA"), + PINCTRL_PIN(125, "SDC2_CLK"), + PINCTRL_PIN(126, "SDC2_CMD"), + PINCTRL_PIN(127, "SDC2_DATA"), + PINCTRL_PIN(128, "QDSD_CLK"), + PINCTRL_PIN(129, "QDSD_CMD"), + PINCTRL_PIN(130, "QDSD_DATA0"), + PINCTRL_PIN(131, "QDSD_DATA1"), + PINCTRL_PIN(132, "QDSD_DATA2"), + PINCTRL_PIN(133, "QDSD_DATA3"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } + +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); + +static const unsigned int sdc1_clk_pins[] = { 122 }; +static const unsigned int sdc1_cmd_pins[] = { 123 }; +static const unsigned int sdc1_data_pins[] = { 124 }; +static const unsigned int sdc2_clk_pins[] = { 125 }; +static const unsigned int sdc2_cmd_pins[] = { 126 }; +static const unsigned int sdc2_data_pins[] = { 127 }; +static const unsigned int qdsd_clk_pins[] = { 128 }; +static const unsigned int qdsd_cmd_pins[] = { 129 }; +static const unsigned int qdsd_data0_pins[] = { 130 }; +static const unsigned int qdsd_data1_pins[] = { 131 }; +static const unsigned int qdsd_data2_pins[] = { 132 }; +static const unsigned int qdsd_data3_pins[] = { 133 }; + +#define FUNCTION(fname) \ + [MSM_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + MSM_MUX_gpio, \ + MSM_MUX_##f1, \ + MSM_MUX_##f2, \ + MSM_MUX_##f3, \ + MSM_MUX_##f4, \ + MSM_MUX_##f5, \ + MSM_MUX_##f6, \ + MSM_MUX_##f7, \ + MSM_MUX_##f8, \ + MSM_MUX_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x4 + 0x1000 * id, \ + .intr_cfg_reg = 0x8 + 0x1000 * id, \ + .intr_status_reg = 0xc + 0x1000 * id, \ + .intr_target_reg = 0x8 + 0x1000 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum msm8916_functions { + MSM_MUX_adsp_ext, + MSM_MUX_alsp_int, + MSM_MUX_atest_bbrx0, + MSM_MUX_atest_bbrx1, + MSM_MUX_atest_char, + MSM_MUX_atest_char0, + MSM_MUX_atest_char1, + MSM_MUX_atest_char2, + MSM_MUX_atest_char3, + MSM_MUX_atest_combodac, + MSM_MUX_atest_gpsadc0, + MSM_MUX_atest_gpsadc1, + MSM_MUX_atest_tsens, + MSM_MUX_atest_wlan0, + MSM_MUX_atest_wlan1, + MSM_MUX_backlight_en, + MSM_MUX_bimc_dte0, + MSM_MUX_bimc_dte1, + MSM_MUX_blsp_i2c1, + MSM_MUX_blsp_i2c2, + MSM_MUX_blsp_i2c3, + MSM_MUX_blsp_i2c4, + MSM_MUX_blsp_i2c5, + MSM_MUX_blsp_i2c6, + MSM_MUX_blsp_spi1, + MSM_MUX_blsp_spi1_cs1, + MSM_MUX_blsp_spi1_cs2, + MSM_MUX_blsp_spi1_cs3, + MSM_MUX_blsp_spi2, + MSM_MUX_blsp_spi2_cs1, + MSM_MUX_blsp_spi2_cs2, + MSM_MUX_blsp_spi2_cs3, + MSM_MUX_blsp_spi3, + MSM_MUX_blsp_spi3_cs1, + MSM_MUX_blsp_spi3_cs2, + MSM_MUX_blsp_spi3_cs3, + MSM_MUX_blsp_spi4, + MSM_MUX_blsp_spi5, + MSM_MUX_blsp_spi6, + MSM_MUX_blsp_uart1, + MSM_MUX_blsp_uart2, + MSM_MUX_blsp_uim1, + MSM_MUX_blsp_uim2, + MSM_MUX_cam1_rst, + MSM_MUX_cam1_standby, + MSM_MUX_cam_mclk0, + MSM_MUX_cam_mclk1, + MSM_MUX_cci_async, + MSM_MUX_cci_i2c, + MSM_MUX_cci_timer0, + MSM_MUX_cci_timer1, + MSM_MUX_cci_timer2, + MSM_MUX_cdc_pdm0, + MSM_MUX_codec_mad, + MSM_MUX_dbg_out, + MSM_MUX_display_5v, + MSM_MUX_dmic0_clk, + MSM_MUX_dmic0_data, + MSM_MUX_dsi_rst, + MSM_MUX_ebi0_wrcdc, + MSM_MUX_euro_us, + MSM_MUX_ext_lpass, + MSM_MUX_flash_strobe, + MSM_MUX_gcc_gp1_clk_a, + MSM_MUX_gcc_gp1_clk_b, + MSM_MUX_gcc_gp2_clk_a, + MSM_MUX_gcc_gp2_clk_b, + MSM_MUX_gcc_gp3_clk_a, + MSM_MUX_gcc_gp3_clk_b, + MSM_MUX_gpio, + MSM_MUX_gsm0_tx0, + MSM_MUX_gsm0_tx1, + MSM_MUX_gsm1_tx0, + MSM_MUX_gsm1_tx1, + MSM_MUX_gyro_accl, + MSM_MUX_kpsns0, + MSM_MUX_kpsns1, + MSM_MUX_kpsns2, + MSM_MUX_ldo_en, + MSM_MUX_ldo_update, + MSM_MUX_mag_int, + MSM_MUX_mdp_vsync, + MSM_MUX_modem_tsync, + MSM_MUX_m_voc, + MSM_MUX_nav_pps, + MSM_MUX_nav_tsync, + MSM_MUX_pa_indicator, + MSM_MUX_pbs0, + MSM_MUX_pbs1, + MSM_MUX_pbs2, + MSM_MUX_pri_mi2s, + MSM_MUX_pri_mi2s_ws, + MSM_MUX_prng_rosc, + MSM_MUX_pwr_crypto_enabled_a, + MSM_MUX_pwr_crypto_enabled_b, + MSM_MUX_pwr_modem_enabled_a, + MSM_MUX_pwr_modem_enabled_b, + MSM_MUX_pwr_nav_enabled_a, + MSM_MUX_pwr_nav_enabled_b, + MSM_MUX_qdss_ctitrig_in_a0, + MSM_MUX_qdss_ctitrig_in_a1, + MSM_MUX_qdss_ctitrig_in_b0, + MSM_MUX_qdss_ctitrig_in_b1, + MSM_MUX_qdss_ctitrig_out_a0, + MSM_MUX_qdss_ctitrig_out_a1, + MSM_MUX_qdss_ctitrig_out_b0, + MSM_MUX_qdss_ctitrig_out_b1, + MSM_MUX_qdss_traceclk_a, + MSM_MUX_qdss_traceclk_b, + MSM_MUX_qdss_tracectl_a, + MSM_MUX_qdss_tracectl_b, + MSM_MUX_qdss_tracedata_a, + MSM_MUX_qdss_tracedata_b, + MSM_MUX_reset_n, + MSM_MUX_sd_card, + MSM_MUX_sd_write, + MSM_MUX_sec_mi2s, + MSM_MUX_smb_int, + MSM_MUX_ssbi_wtr0, + MSM_MUX_ssbi_wtr1, + MSM_MUX_uim1, + MSM_MUX_uim2, + MSM_MUX_uim3, + MSM_MUX_uim_batt, + MSM_MUX_wcss_bt, + MSM_MUX_wcss_fm, + MSM_MUX_wcss_wlan, + MSM_MUX_webcam1_rst, + MSM_MUX_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121" +}; +static const char * const adsp_ext_groups[] = { "gpio38" }; +static const char * const alsp_int_groups[] = { "gpio113" }; +static const char * const atest_bbrx0_groups[] = { "gpio17" }; +static const char * const atest_bbrx1_groups[] = { "gpio16" }; +static const char * const atest_char_groups[] = { "gpio62" }; +static const char * const atest_char0_groups[] = { "gpio60" }; +static const char * const atest_char1_groups[] = { "gpio59" }; +static const char * const atest_char2_groups[] = { "gpio58" }; +static const char * const atest_char3_groups[] = { "gpio57" }; +static const char * const atest_combodac_groups[] = { + "gpio4", "gpio12", "gpio13", "gpio20", "gpio21", "gpio28", "gpio29", + "gpio30", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", + "gpio45", "gpio46", "gpio47", "gpio48", "gpio69", "gpio107" +}; +static const char * const atest_gpsadc0_groups[] = { "gpio7" }; +static const char * const atest_gpsadc1_groups[] = { "gpio18" }; +static const char * const atest_tsens_groups[] = { "gpio112" }; +static const char * const atest_wlan0_groups[] = { "gpio22" }; +static const char * const atest_wlan1_groups[] = { "gpio23" }; +static const char * const backlight_en_groups[] = { "gpio98" }; +static const char * const bimc_dte0_groups[] = { "gpio63", "gpio65" }; +static const char * const bimc_dte1_groups[] = { "gpio64", "gpio66" }; +static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" }; +static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; +static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" }; +static const char * const blsp_i2c4_groups[] = { "gpio14", "gpio15" }; +static const char * const blsp_i2c5_groups[] = { "gpio18", "gpio19" }; +static const char * const blsp_i2c6_groups[] = { "gpio22", "gpio23" }; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_spi1_cs1_groups[] = { "gpio110" }; +static const char * const blsp_spi1_cs2_groups[] = { "gpio16" }; +static const char * const blsp_spi1_cs3_groups[] = { "gpio4" }; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_spi2_cs1_groups[] = { "gpio121" }; +static const char * const blsp_spi2_cs2_groups[] = { "gpio17" }; +static const char * const blsp_spi2_cs3_groups[] = { "gpio5" }; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char * const blsp_spi3_cs1_groups[] = { "gpio120" }; +static const char * const blsp_spi3_cs2_groups[] = { "gpio37" }; +static const char * const blsp_spi3_cs3_groups[] = { "gpio69" }; +static const char * const blsp_spi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15" +}; +static const char * const blsp_spi5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19" +}; +static const char * const blsp_spi6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23" +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" }; +static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" }; +static const char * const cam1_rst_groups[] = { "gpio35" }; +static const char * const cam1_standby_groups[] = { "gpio34" }; +static const char * const cam_mclk0_groups[] = { "gpio26" }; +static const char * const cam_mclk1_groups[] = { "gpio27" }; +static const char * const cci_async_groups[] = { "gpio33" }; +static const char * const cci_i2c_groups[] = { "gpio29", "gpio30" }; +static const char * const cci_timer0_groups[] = { "gpio31" }; +static const char * const cci_timer1_groups[] = { "gpio32" }; +static const char * const cci_timer2_groups[] = { "gpio38" }; +static const char * const cdc_pdm0_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; +static const char * const codec_mad_groups[] = { "gpio16" }; +static const char * const dbg_out_groups[] = { "gpio47" }; +static const char * const display_5v_groups[] = { "gpio97" }; +static const char * const dmic0_clk_groups[] = { "gpio0" }; +static const char * const dmic0_data_groups[] = { "gpio1" }; +static const char * const dsi_rst_groups[] = { "gpio25" }; +static const char * const ebi0_wrcdc_groups[] = { "gpio67" }; +static const char * const euro_us_groups[] = { "gpio120" }; +static const char * const ext_lpass_groups[] = { "gpio45" }; +static const char * const flash_strobe_groups[] = { "gpio31", "gpio32" }; +static const char * const gcc_gp1_clk_a_groups[] = { "gpio49" }; +static const char * const gcc_gp1_clk_b_groups[] = { "gpio97" }; +static const char * const gcc_gp2_clk_a_groups[] = { "gpio50" }; +static const char * const gcc_gp2_clk_b_groups[] = { "gpio12" }; +static const char * const gcc_gp3_clk_a_groups[] = { "gpio51" }; +static const char * const gcc_gp3_clk_b_groups[] = { "gpio13" }; +static const char * const gsm0_tx0_groups[] = { "gpio99" }; +static const char * const gsm0_tx1_groups[] = { "gpio100" }; +static const char * const gsm1_tx0_groups[] = { "gpio101" }; +static const char * const gsm1_tx1_groups[] = { "gpio102" }; +static const char * const gyro_accl_groups[] = {"gpio115" }; +static const char * const kpsns0_groups[] = { "gpio107" }; +static const char * const kpsns1_groups[] = { "gpio108" }; +static const char * const kpsns2_groups[] = { "gpio109" }; +static const char * const ldo_en_groups[] = { "gpio121" }; +static const char * const ldo_update_groups[] = { "gpio120" }; +static const char * const mag_int_groups[] = { "gpio69" }; +static const char * const mdp_vsync_groups[] = { "gpio24", "gpio25" }; +static const char * const modem_tsync_groups[] = { "gpio95" }; +static const char * const m_voc_groups[] = { "gpio8", "gpio119" }; +static const char * const nav_pps_groups[] = { "gpio95" }; +static const char * const nav_tsync_groups[] = { "gpio95" }; +static const char * const pa_indicator_groups[] = { "gpio86" }; +static const char * const pbs0_groups[] = { "gpio107" }; +static const char * const pbs1_groups[] = { "gpio108" }; +static const char * const pbs2_groups[] = { "gpio109" }; +static const char * const pri_mi2s_groups[] = { + "gpio113", "gpio114", "gpio115", "gpio116" +}; +static const char * const pri_mi2s_ws_groups[] = { "gpio110" }; +static const char * const prng_rosc_groups[] = { "gpio43" }; +static const char * const pwr_crypto_enabled_a_groups[] = { "gpio35" }; +static const char * const pwr_crypto_enabled_b_groups[] = { "gpio115" }; +static const char * const pwr_modem_enabled_a_groups[] = { "gpio28" }; +static const char * const pwr_modem_enabled_b_groups[] = { "gpio113" }; +static const char * const pwr_nav_enabled_a_groups[] = { "gpio34" }; +static const char * const pwr_nav_enabled_b_groups[] = { "gpio114" }; +static const char * const qdss_ctitrig_in_a0_groups[] = { "gpio20" }; +static const char * const qdss_ctitrig_in_a1_groups[] = { "gpio49" }; +static const char * const qdss_ctitrig_in_b0_groups[] = { "gpio21" }; +static const char * const qdss_ctitrig_in_b1_groups[] = { "gpio50" }; +static const char * const qdss_ctitrig_out_a0_groups[] = { "gpio23" }; +static const char * const qdss_ctitrig_out_a1_groups[] = { "gpio52" }; +static const char * const qdss_ctitrig_out_b0_groups[] = { "gpio22" }; +static const char * const qdss_ctitrig_out_b1_groups[] = { "gpio51" }; +static const char * const qdss_traceclk_a_groups[] = { "gpio46" }; +static const char * const qdss_traceclk_b_groups[] = { "gpio5" }; +static const char * const qdss_tracectl_a_groups[] = { "gpio45" }; +static const char * const qdss_tracectl_b_groups[] = { "gpio4" }; +static const char * const qdss_tracedata_a_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio47", "gpio48", "gpio62", "gpio69", "gpio112", "gpio113", + "gpio114", "gpio115" +}; +static const char * const qdss_tracedata_b_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio110", "gpio111", + "gpio120", "gpio121" +}; +static const char * const reset_n_groups[] = { "gpio36" }; +static const char * const sd_card_groups[] = { "gpio38" }; +static const char * const sd_write_groups[] = { "gpio121" }; +static const char * const sec_mi2s_groups[] = { + "gpio112", "gpio117", "gpio118", "gpio119" +}; +static const char * const smb_int_groups[] = { "gpio62" }; +static const char * const ssbi_wtr0_groups[] = { "gpio103", "gpio104" }; +static const char * const ssbi_wtr1_groups[] = { "gpio105", "gpio106" }; +static const char * const uim1_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60" +}; + +static const char * const uim2_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const uim3_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char * const uim_batt_groups[] = { "gpio61" }; +static const char * const wcss_bt_groups[] = { "gpio39", "gpio47", "gpio48" }; +static const char * const wcss_fm_groups[] = { "gpio45", "gpio46" }; +static const char * const wcss_wlan_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44" +}; +static const char * const webcam1_rst_groups[] = { "gpio28" }; + +static const struct msm_function msm8916_functions[] = { + FUNCTION(adsp_ext), + FUNCTION(alsp_int), + FUNCTION(atest_bbrx0), + FUNCTION(atest_bbrx1), + FUNCTION(atest_char), + FUNCTION(atest_char0), + FUNCTION(atest_char1), + FUNCTION(atest_char2), + FUNCTION(atest_char3), + FUNCTION(atest_combodac), + FUNCTION(atest_gpsadc0), + FUNCTION(atest_gpsadc1), + FUNCTION(atest_tsens), + FUNCTION(atest_wlan0), + FUNCTION(atest_wlan1), + FUNCTION(backlight_en), + FUNCTION(bimc_dte0), + FUNCTION(bimc_dte1), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c4), + FUNCTION(blsp_i2c5), + FUNCTION(blsp_i2c6), + FUNCTION(blsp_spi1), + FUNCTION(blsp_spi1_cs1), + FUNCTION(blsp_spi1_cs2), + FUNCTION(blsp_spi1_cs3), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi2_cs1), + FUNCTION(blsp_spi2_cs2), + FUNCTION(blsp_spi2_cs3), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi3_cs1), + FUNCTION(blsp_spi3_cs2), + FUNCTION(blsp_spi3_cs3), + FUNCTION(blsp_spi4), + FUNCTION(blsp_spi5), + FUNCTION(blsp_spi6), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uim1), + FUNCTION(blsp_uim2), + FUNCTION(cam1_rst), + FUNCTION(cam1_standby), + FUNCTION(cam_mclk0), + FUNCTION(cam_mclk1), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cdc_pdm0), + FUNCTION(codec_mad), + FUNCTION(dbg_out), + FUNCTION(display_5v), + FUNCTION(dmic0_clk), + FUNCTION(dmic0_data), + FUNCTION(dsi_rst), + FUNCTION(ebi0_wrcdc), + FUNCTION(euro_us), + FUNCTION(ext_lpass), + FUNCTION(flash_strobe), + FUNCTION(gcc_gp1_clk_a), + FUNCTION(gcc_gp1_clk_b), + FUNCTION(gcc_gp2_clk_a), + FUNCTION(gcc_gp2_clk_b), + FUNCTION(gcc_gp3_clk_a), + FUNCTION(gcc_gp3_clk_b), + FUNCTION(gpio), + FUNCTION(gsm0_tx0), + FUNCTION(gsm0_tx1), + FUNCTION(gsm1_tx0), + FUNCTION(gsm1_tx1), + FUNCTION(gyro_accl), + FUNCTION(kpsns0), + FUNCTION(kpsns1), + FUNCTION(kpsns2), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(mag_int), + FUNCTION(mdp_vsync), + FUNCTION(modem_tsync), + FUNCTION(m_voc), + FUNCTION(nav_pps), + FUNCTION(nav_tsync), + FUNCTION(pa_indicator), + FUNCTION(pbs0), + FUNCTION(pbs1), + FUNCTION(pbs2), + FUNCTION(pri_mi2s), + FUNCTION(pri_mi2s_ws), + FUNCTION(prng_rosc), + FUNCTION(pwr_crypto_enabled_a), + FUNCTION(pwr_crypto_enabled_b), + FUNCTION(pwr_modem_enabled_a), + FUNCTION(pwr_modem_enabled_b), + FUNCTION(pwr_nav_enabled_a), + FUNCTION(pwr_nav_enabled_b), + FUNCTION(qdss_ctitrig_in_a0), + FUNCTION(qdss_ctitrig_in_a1), + FUNCTION(qdss_ctitrig_in_b0), + FUNCTION(qdss_ctitrig_in_b1), + FUNCTION(qdss_ctitrig_out_a0), + FUNCTION(qdss_ctitrig_out_a1), + FUNCTION(qdss_ctitrig_out_b0), + FUNCTION(qdss_ctitrig_out_b1), + FUNCTION(qdss_traceclk_a), + FUNCTION(qdss_traceclk_b), + FUNCTION(qdss_tracectl_a), + FUNCTION(qdss_tracectl_b), + FUNCTION(qdss_tracedata_a), + FUNCTION(qdss_tracedata_b), + FUNCTION(reset_n), + FUNCTION(sd_card), + FUNCTION(sd_write), + FUNCTION(sec_mi2s), + FUNCTION(smb_int), + FUNCTION(ssbi_wtr0), + FUNCTION(ssbi_wtr1), + FUNCTION(uim1), + FUNCTION(uim2), + FUNCTION(uim3), + FUNCTION(uim_batt), + FUNCTION(wcss_bt), + FUNCTION(wcss_fm), + FUNCTION(wcss_wlan), + FUNCTION(webcam1_rst) +}; + +static const struct msm_pingroup msm8916_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, dmic0_clk, NA, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, dmic0_data, NA, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, blsp_spi1_cs3, qdss_tracectl_b, NA, atest_combodac, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, blsp_spi2_cs3, qdss_traceclk_b, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, m_voc, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(9, blsp_spi3, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, blsp_spi3, blsp_i2c3, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_i2c3, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(12, blsp_spi4, gcc_gp2_clk_b, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(13, blsp_spi4, gcc_gp3_clk_b, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(14, blsp_spi4, blsp_i2c4, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, blsp_spi4, blsp_i2c4, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, blsp_spi5, blsp_spi1_cs2, NA, atest_bbrx1, NA, NA, NA, NA, NA), + PINGROUP(17, blsp_spi5, blsp_spi2_cs2, NA, atest_bbrx0, NA, NA, NA, NA, NA), + PINGROUP(18, blsp_spi5, blsp_i2c5, NA, atest_gpsadc1, NA, NA, NA, NA, NA), + PINGROUP(19, blsp_spi5, blsp_i2c5, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, blsp_spi6, NA, NA, NA, NA, NA, NA, qdss_ctitrig_in_a0, NA), + PINGROUP(21, blsp_spi6, NA, NA, NA, NA, NA, NA, qdss_ctitrig_in_b0, NA), + PINGROUP(22, blsp_spi6, blsp_i2c6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, blsp_spi6, blsp_i2c6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, cam_mclk0, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(27, cam_mclk1, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(28, pwr_modem_enabled_a, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac), + PINGROUP(29, cci_i2c, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac), + PINGROUP(30, cci_i2c, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(31, cci_timer0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, cci_timer1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, cci_async, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(34, pwr_nav_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(35, pwr_crypto_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA), + PINGROUP(37, blsp_spi3_cs2, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(38, cci_timer2, adsp_ext, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, wcss_bt, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(40, wcss_wlan, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(41, wcss_wlan, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(42, wcss_wlan, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(43, wcss_wlan, prng_rosc, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA), + PINGROUP(44, wcss_wlan, NA, atest_combodac, NA, NA, NA, NA, NA, NA), + PINGROUP(45, wcss_fm, ext_lpass, qdss_tracectl_a, NA, atest_combodac, NA, NA, NA, NA), + PINGROUP(46, wcss_fm, qdss_traceclk_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(47, wcss_bt, dbg_out, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA), + PINGROUP(48, wcss_bt, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(49, uim3, gcc_gp1_clk_a, qdss_ctitrig_in_a1, NA, NA, NA, NA, NA, NA), + PINGROUP(50, uim3, gcc_gp2_clk_a, qdss_ctitrig_in_b1, NA, NA, NA, NA, NA, NA), + PINGROUP(51, uim3, gcc_gp3_clk_a, qdss_ctitrig_out_b1, NA, NA, NA, NA, NA, NA), + PINGROUP(52, uim3, NA, qdss_ctitrig_out_a1, NA, NA, NA, NA, NA, NA), + PINGROUP(53, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, uim1, atest_char3, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, uim1, atest_char2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, uim1, atest_char1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, uim1, atest_char0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, atest_char, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, cdc_pdm0, bimc_dte0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, cdc_pdm0, bimc_dte1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, cdc_pdm0, bimc_dte0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, cdc_pdm0, bimc_dte1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, cdc_pdm0, ebi0_wrcdc, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, blsp_spi3_cs3, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, pa_indicator, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(93, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, NA, modem_tsync, nav_tsync, nav_pps, NA, NA, NA, NA, NA), + PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, gcc_gp1_clk_b, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(99, gsm0_tx0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, gsm0_tx1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, gsm1_tx0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, gsm1_tx1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, ssbi_wtr0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, ssbi_wtr0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, ssbi_wtr1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, ssbi_wtr1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, pbs0, NA, atest_combodac, NA, NA, NA, NA, NA, NA), + PINGROUP(108, pbs1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, pbs2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, blsp_spi1_cs1, pri_mi2s_ws, NA, qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(111, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, sec_mi2s, NA, NA, NA, qdss_tracedata_a, NA, atest_tsens, NA, NA), + PINGROUP(113, pri_mi2s, NA, pwr_modem_enabled_b, NA, NA, NA, NA, NA, qdss_tracedata_a), + PINGROUP(114, pri_mi2s, pwr_nav_enabled_b, NA, NA, NA, NA, NA, qdss_tracedata_a, NA), + PINGROUP(115, pri_mi2s, pwr_crypto_enabled_b, NA, NA, NA, NA, NA, qdss_tracedata_a, NA), + PINGROUP(116, pri_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(117, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(118, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(119, sec_mi2s, m_voc, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(120, blsp_spi3_cs1, ldo_update, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(121, sd_write, blsp_spi2_cs1, ldo_en, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc1_clk, 0x10a000, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x10a000, 11, 3), + SDC_PINGROUP(sdc1_data, 0x10a000, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x109000, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x109000, 11, 3), + SDC_PINGROUP(sdc2_data, 0x109000, 9, 0), + SDC_PINGROUP(qdsd_clk, 0x19c000, 3, 0), + SDC_PINGROUP(qdsd_cmd, 0x19c000, 8, 5), + SDC_PINGROUP(qdsd_data0, 0x19c000, 13, 10), + SDC_PINGROUP(qdsd_data1, 0x19c000, 18, 15), + SDC_PINGROUP(qdsd_data2, 0x19c000, 23, 20), + SDC_PINGROUP(qdsd_data3, 0x19c000, 28, 25), +}; + +#define NUM_GPIO_PINGROUPS 122 + +static const struct msm_pinctrl_soc_data msm8916_pinctrl = { + .pins = msm8916_pins, + .npins = ARRAY_SIZE(msm8916_pins), + .functions = msm8916_functions, + .nfunctions = ARRAY_SIZE(msm8916_functions), + .groups = msm8916_groups, + .ngroups = ARRAY_SIZE(msm8916_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8916_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8916_pinctrl); +} + +static const struct of_device_id msm8916_pinctrl_of_match[] = { + { .compatible = "qcom,msm8916-pinctrl", }, + { }, +}; + +static struct platform_driver msm8916_pinctrl_driver = { + .driver = { + .name = "msm8916-pinctrl", + .of_match_table = msm8916_pinctrl_of_match, + }, + .probe = msm8916_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8916_pinctrl_init(void) +{ + return platform_driver_register(&msm8916_pinctrl_driver); +} +arch_initcall(msm8916_pinctrl_init); + +static void __exit msm8916_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8916_pinctrl_driver); +} +module_exit(msm8916_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm msm8916 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8916_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index b863b5080890..0f11a26d932b 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -131,15 +131,17 @@ struct pmic_gpio_state { struct gpio_chip chip; }; -struct pmic_gpio_bindings { - const char *property; - unsigned param; +static const struct pinconf_generic_params pmic_gpio_bindings[] = { + {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0}, + {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0}, }; -static struct pmic_gpio_bindings pmic_gpio_bindings[] = { - {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP}, - {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH}, +#ifdef CONFIG_DEBUG_FS +static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { + PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true), + PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true), }; +#endif static const char *const pmic_gpio_groups[] = { "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", @@ -209,118 +211,11 @@ static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin, return 0; } -static int pmic_gpio_parse_dt_config(struct device_node *np, - struct pinctrl_dev *pctldev, - unsigned long **configs, - unsigned int *nconfs) -{ - struct pmic_gpio_bindings *par; - unsigned long cfg; - int ret, i; - u32 val; - - for (i = 0; i < ARRAY_SIZE(pmic_gpio_bindings); i++) { - par = &pmic_gpio_bindings[i]; - ret = of_property_read_u32(np, par->property, &val); - - /* property not found */ - if (ret == -EINVAL) - continue; - - /* use zero as default value */ - if (ret) - val = 0; - - dev_dbg(pctldev->dev, "found %s with value %u\n", - par->property, val); - - cfg = pinconf_to_config_packed(par->param, val); - - ret = pinctrl_utils_add_config(pctldev, configs, nconfs, cfg); - if (ret) - return ret; - } - - return 0; -} - -static int pmic_gpio_dt_subnode_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, - unsigned *reserv, unsigned *nmaps, - enum pinctrl_map_type type) -{ - unsigned long *configs = NULL; - unsigned nconfs = 0; - struct property *prop; - const char *group; - int ret; - - ret = pmic_gpio_parse_dt_config(np, pctldev, &configs, &nconfs); - if (ret < 0) - return ret; - - if (!nconfs) - return 0; - - ret = of_property_count_strings(np, "pins"); - if (ret < 0) - goto exit; - - ret = pinctrl_utils_reserve_map(pctldev, map, reserv, nmaps, ret); - if (ret < 0) - goto exit; - - of_property_for_each_string(np, "pins", prop, group) { - ret = pinctrl_utils_add_map_configs(pctldev, map, - reserv, nmaps, group, - configs, nconfs, type); - if (ret < 0) - break; - } -exit: - kfree(configs); - return ret; -} - -static int pmic_gpio_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, unsigned *nmaps) -{ - enum pinctrl_map_type type; - struct device_node *np; - unsigned reserv; - int ret; - - ret = 0; - *map = NULL; - *nmaps = 0; - reserv = 0; - type = PIN_MAP_TYPE_CONFIGS_GROUP; - - for_each_child_of_node(np_config, np) { - ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map, - &reserv, nmaps, type); - if (ret) - break; - - ret = pmic_gpio_dt_subnode_to_map(pctldev, np, map, &reserv, - nmaps, type); - if (ret) - break; - } - - if (ret < 0) - pinctrl_utils_dt_free_map(pctldev, *map, *nmaps); - - return ret; -} - static const struct pinctrl_ops pmic_gpio_pinctrl_ops = { .get_groups_count = pmic_gpio_get_groups_count, .get_group_name = pmic_gpio_get_group_name, .get_group_pins = pmic_gpio_get_group_pins, - .dt_node_to_map = pmic_gpio_dt_node_to_map, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, .dt_free_map = pinctrl_utils_dt_free_map, }; @@ -590,6 +485,7 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, } static const struct pinconf_ops pmic_gpio_pinconf_ops = { + .is_generic = true, .pin_config_group_get = pmic_gpio_config_get, .pin_config_group_set = pmic_gpio_config_set, .pin_config_group_dbg_show = pmic_gpio_config_dbg_show, @@ -848,6 +744,11 @@ static int pmic_gpio_probe(struct platform_device *pdev) pctrldesc->name = dev_name(dev); pctrldesc->pins = pindesc; pctrldesc->npins = npins; + pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings); + pctrldesc->custom_params = pmic_gpio_bindings; +#ifdef CONFIG_DEBUG_FS + pctrldesc->custom_conf_items = pmic_conf_items; +#endif for (i = 0; i < npins; i++, pindesc++) { pad = &pads[i]; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index becb3792977b..c8f83f96546c 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -1300,6 +1300,25 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c), }; +/* pin banks of exynos7 pin-controller - BUS1 */ +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14), + EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18), + EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c), + EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20), + EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24), +}; + +static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { { /* pin-controller instance 0 Alive data */ @@ -1342,5 +1361,15 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { .pin_banks = exynos7_pin_banks7, .nr_banks = ARRAY_SIZE(exynos7_pin_banks7), .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 8 BUS1 data */ + .pin_banks = exynos7_pin_banks8, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks8), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 9 AUD data */ + .pin_banks = exynos7_pin_banks9, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks9), + .eint_gpio_init = exynos_eint_gpio_init, }, }; diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 26187aa5cf5b..8c4b3d391823 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -20,6 +20,11 @@ config GPIO_SH_PFC This enables support for GPIOs within the SoC's pin function controller. +config PINCTRL_PFC_EMEV2 + def_bool y + depends on ARCH_EMEV2 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A73A4 def_bool y depends on ARCH_R8A73A4 @@ -68,11 +73,6 @@ config PINCTRL_PFC_SH7269 depends on GPIOLIB select PINCTRL_SH_PFC -config PINCTRL_PFC_SH7372 - def_bool y - depends on ARCH_SH7372 - select PINCTRL_SH_PFC - config PINCTRL_PFC_SH73A0 def_bool y depends on ARCH_SH73A0 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index ad8f4cf9faaa..f4074e166bcf 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -3,6 +3,7 @@ ifeq ($(CONFIG_GPIO_SH_PFC),y) sh-pfc-objs += gpio.o endif obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o +obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o @@ -12,7 +13,6 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o -obj-$(CONFIG_PINCTRL_PFC_SH7372) += pfc-sh7372.o obj-$(CONFIG_PINCTRL_PFC_SH73A0) += pfc-sh73a0.o obj-$(CONFIG_PINCTRL_PFC_SH7720) += pfc-sh7720.o obj-$(CONFIG_PINCTRL_PFC_SH7722) += pfc-sh7722.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 66dc62d2156c..a56280814a3f 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -439,6 +439,12 @@ static int sh_pfc_init_ranges(struct sh_pfc *pfc) #ifdef CONFIG_OF static const struct of_device_id sh_pfc_of_table[] = { +#ifdef CONFIG_PINCTRL_PFC_EMEV2 + { + .compatible = "renesas,pfc-emev2", + .data = &emev2_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A73A4 { .compatible = "renesas,pfc-r8a73a4", @@ -475,12 +481,6 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7791_pinmux_info, }, #endif -#ifdef CONFIG_PINCTRL_PFC_SH7372 - { - .compatible = "renesas,pfc-sh7372", - .data = &sh7372_pinmux_info, - }, -#endif #ifdef CONFIG_PINCTRL_PFC_SH73A0 { .compatible = "renesas,pfc-sh73a0", @@ -579,6 +579,9 @@ static int sh_pfc_remove(struct platform_device *pdev) } static const struct platform_device_id sh_pfc_id_table[] = { +#ifdef CONFIG_PINCTRL_PFC_EMEV2 + { "pfc-emev2", (kernel_ulong_t)&emev2_pinmux_info }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A73A4 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info }, #endif @@ -606,9 +609,6 @@ static const struct platform_device_id sh_pfc_id_table[] = { #ifdef CONFIG_PINCTRL_PFC_SH7269 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info }, #endif -#ifdef CONFIG_PINCTRL_PFC_SH7372 - { "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info }, -#endif #ifdef CONFIG_PINCTRL_PFC_SH73A0 { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info }, #endif diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 3daaa5241c47..6b59d63b9c01 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -65,6 +65,7 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); +extern const struct sh_pfc_soc_info emev2_pinmux_info; extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; extern const struct sh_pfc_soc_info r8a7740_pinmux_info; extern const struct sh_pfc_soc_info r8a7778_pinmux_info; @@ -74,7 +75,6 @@ extern const struct sh_pfc_soc_info r8a7791_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; -extern const struct sh_pfc_soc_info sh7372_pinmux_info; extern const struct sh_pfc_soc_info sh73a0_pinmux_info; extern const struct sh_pfc_soc_info sh7720_pinmux_info; extern const struct sh_pfc_soc_info sh7722_pinmux_info; diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/sh-pfc/pfc-emev2.c new file mode 100644 index 000000000000..849c6943ed30 --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-emev2.c @@ -0,0 +1,1711 @@ +/* + * Pin Function Controller Support + * + * Copyright (C) 2015 Niklas Söderlund + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/kernel.h> + +#include "sh_pfc.h" + +#define CPU_ALL_PORT(fn, pfx, sfx) \ + PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \ + PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \ + PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \ + PORT_10(140, fn, pfx##14, sfx), PORT_1(150, fn, pfx##150, sfx), \ + PORT_1(151, fn, pfx##151, sfx), PORT_1(152, fn, pfx##152, sfx), \ + PORT_1(153, fn, pfx##153, sfx), PORT_1(154, fn, pfx##154, sfx), \ + PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \ + PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PORT_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_FUNCTION_BEGIN, + PORT_ALL(FN), + + /* GPSR0 */ + FN_LCD3_1_0_PORT18, FN_LCD3_1_0_PORT20, FN_LCD3_1_0_PORT21, + FN_LCD3_1_0_PORT22, FN_LCD3_1_0_PORT23, + FN_JT_SEL, FN_ERR_RST_REQB, FN_REF_CLKO, FN_EXT_CLKI, FN_LCD3_PXCLKB, + + /* GPSR1 */ + FN_LCD3_9_8_PORT38, FN_LCD3_9_8_PORT39, FN_LCD3_11_10_PORT40, + FN_LCD3_11_10_PORT41, FN_LCD3_11_10_PORT42, FN_LCD3_11_10_PORT43, + FN_IIC_1_0_PORT46, FN_IIC_1_0_PORT47, + FN_LCD3_R0, FN_LCD3_R1, FN_LCD3_R2, FN_LCD3_R3, FN_LCD3_R4, FN_LCD3_R5, + FN_IIC0_SCL, FN_IIC0_SDA, FN_SD_CKI, FN_SDI0_CKO, FN_SDI0_CKI, + FN_SDI0_CMD, FN_SDI0_DATA0, FN_SDI0_DATA1, FN_SDI0_DATA2, + FN_SDI0_DATA3, FN_SDI0_DATA4, FN_SDI0_DATA5, FN_SDI0_DATA6, + FN_SDI0_DATA7, FN_SDI1_CKO, FN_SDI1_CKI, FN_SDI1_CMD, + + /* GPSR2 */ + FN_AB_1_0_PORT71, FN_AB_1_0_PORT72, FN_AB_1_0_PORT73, + FN_AB_1_0_PORT74, FN_AB_1_0_PORT75, FN_AB_1_0_PORT76, + FN_AB_1_0_PORT77, FN_AB_1_0_PORT78, FN_AB_1_0_PORT79, + FN_AB_1_0_PORT80, FN_AB_1_0_PORT81, FN_AB_1_0_PORT82, + FN_AB_1_0_PORT83, FN_AB_1_0_PORT84, FN_AB_3_2_PORT85, + FN_AB_3_2_PORT86, FN_AB_3_2_PORT87, FN_AB_3_2_PORT88, + FN_AB_5_4_PORT89, FN_AB_5_4_PORT90, FN_AB_7_6_PORT91, + FN_AB_7_6_PORT92, FN_AB_1_0_PORT93, FN_AB_1_0_PORT94, + FN_AB_1_0_PORT95, + FN_SDI1_DATA0, FN_SDI1_DATA1, FN_SDI1_DATA2, FN_SDI1_DATA3, + FN_AB_CLK, FN_AB_CSB0, FN_AB_CSB1, + + /* GPSR3 */ + FN_AB_13_12_PORT104, FN_AB_13_12_PORT103, FN_AB_11_10_PORT102, + FN_AB_11_10_PORT101, FN_AB_11_10_PORT100, FN_AB_9_8_PORT99, + FN_AB_9_8_PORT98, FN_AB_9_8_PORT97, + FN_USI_1_0_PORT109, FN_USI_1_0_PORT110, FN_USI_1_0_PORT111, + FN_USI_1_0_PORT112, FN_USI_3_2_PORT113, FN_USI_3_2_PORT114, + FN_USI_5_4_PORT115, FN_USI_5_4_PORT116, FN_USI_5_4_PORT117, + FN_USI_5_4_PORT118, FN_USI_7_6_PORT119, FN_USI_9_8_PORT120, + FN_USI_9_8_PORT121, + FN_AB_A20, FN_USI0_CS1, FN_USI0_CS2, FN_USI1_DI, + FN_USI1_DO, + FN_NTSC_CLK, FN_NTSC_DATA0, FN_NTSC_DATA1, FN_NTSC_DATA2, + FN_NTSC_DATA3, FN_NTSC_DATA4, + + /* GPRS4 */ + FN_HSI_1_0_PORT143, FN_HSI_1_0_PORT144, FN_HSI_1_0_PORT145, + FN_HSI_1_0_PORT146, FN_HSI_1_0_PORT147, FN_HSI_1_0_PORT148, + FN_HSI_1_0_PORT149, FN_HSI_1_0_PORT150, + FN_UART_1_0_PORT157, FN_UART_1_0_PORT158, + FN_NTSC_DATA5, FN_NTSC_DATA6, FN_NTSC_DATA7, FN_CAM_CLKO, + FN_CAM_CLKI, FN_CAM_VS, FN_CAM_HS, FN_CAM_YUV0, + FN_CAM_YUV1, FN_CAM_YUV2, FN_CAM_YUV3, FN_CAM_YUV4, + FN_CAM_YUV5, FN_CAM_YUV6, FN_CAM_YUV7, + FN_JT_TDO, FN_JT_TDOEN, FN_LOWPWR, FN_USB_VBUS, FN_UART1_RX, + FN_UART1_TX, + + /* CHG_PINSEL_LCD3 */ + FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, + FN_SEL_LCD3_9_8_00, FN_SEL_LCD3_9_8_10, + FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01, FN_SEL_LCD3_11_10_10, + + /* CHG_PINSEL_IIC */ + FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, + + /* CHG_PINSEL_AB */ + FN_SEL_AB_1_0_00, FN_SEL_AB_1_0_10, FN_SEL_AB_3_2_00, + FN_SEL_AB_3_2_01, FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11, + FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01, FN_SEL_AB_5_4_10, + FN_SEL_AB_5_4_11, FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01, + FN_SEL_AB_7_6_10, + FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10, + FN_SEL_AB_11_10_00, FN_SEL_AB_11_10_10, + FN_SEL_AB_13_12_00, FN_SEL_AB_13_12_10, + + /* CHG_PINSEL_USI */ + FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, + FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, + FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01, + FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01, + FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01, + + /* CHG_PINSEL_HSI */ + FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, + + /* CHG_PINSEL_UART */ + FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, + + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + /* GPSR0 */ + JT_SEL_MARK, ERR_RST_REQB_MARK, REF_CLKO_MARK, EXT_CLKI_MARK, + LCD3_PXCLKB_MARK, SD_CKI_MARK, + + /* GPSR1 */ + LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK, LCD3_R4_MARK, + LCD3_R5_MARK, IIC0_SCL_MARK, IIC0_SDA_MARK, SDI0_CKO_MARK, + SDI0_CKI_MARK, SDI0_CMD_MARK, SDI0_DATA0_MARK, SDI0_DATA1_MARK, + SDI0_DATA2_MARK, SDI0_DATA3_MARK, SDI0_DATA4_MARK, SDI0_DATA5_MARK, + SDI0_DATA6_MARK, SDI0_DATA7_MARK, SDI1_CKO_MARK, SDI1_CKI_MARK, + SDI1_CMD_MARK, + + /* GPSR2 */ + SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK, + AB_CLK_MARK, AB_CSB0_MARK, AB_CSB1_MARK, + + /* GPSR3 */ + AB_A20_MARK, USI0_CS1_MARK, USI0_CS2_MARK, USI1_DI_MARK, + USI1_DO_MARK, + NTSC_CLK_MARK, NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK, + NTSC_DATA3_MARK, NTSC_DATA4_MARK, + + /* GPSR3 */ + NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK, CAM_CLKO_MARK, + CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK, CAM_YUV0_MARK, + CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK, CAM_YUV4_MARK, + CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK, + JT_TDO_MARK, JT_TDOEN_MARK, USB_VBUS_MARK, LOWPWR_MARK, + UART1_RX_MARK, UART1_TX_MARK, + + /* CHG_PINSEL_LCD3 */ + LCD3_PXCLK_MARK, LCD3_CLK_I_MARK, LCD3_HS_MARK, LCD3_VS_MARK, + LCD3_DE_MARK, LCD3_R6_MARK, LCD3_R7_MARK, LCD3_G0_MARK, LCD3_G1_MARK, + LCD3_G2_MARK, LCD3_G3_MARK, LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK, + LCD3_G7_MARK, LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK, + LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK, + YUV3_CLK_O_MARK, YUV3_CLK_I_MARK, YUV3_HS_MARK, YUV3_VS_MARK, + YUV3_DE_MARK, YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK, + YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK, YUV3_D8_MARK, + YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK, YUV3_D12_MARK, + YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK, + TP33_CLK_MARK, TP33_CTRL_MARK, TP33_DATA0_MARK, TP33_DATA1_MARK, + TP33_DATA2_MARK, TP33_DATA3_MARK, TP33_DATA4_MARK, TP33_DATA5_MARK, + TP33_DATA6_MARK, TP33_DATA7_MARK, TP33_DATA8_MARK, TP33_DATA9_MARK, + TP33_DATA10_MARK, TP33_DATA11_MARK, TP33_DATA12_MARK, TP33_DATA13_MARK, + TP33_DATA14_MARK, TP33_DATA15_MARK, + + /* CHG_PINSEL_IIC */ + IIC1_SCL_MARK, IIC1_SDA_MARK, UART3_RX_MARK, UART3_TX_MARK, + + /* CHG_PINSEL_AB */ + AB_CSB2_MARK, AB_CSB3_MARK, AB_RDB_MARK, AB_WRB_MARK, + AB_WAIT_MARK, AB_ADV_MARK, AB_AD0_MARK, AB_AD1_MARK, + AB_AD2_MARK, AB_AD3_MARK, AB_AD4_MARK, AB_AD5_MARK, + AB_AD6_MARK, AB_AD7_MARK, AB_AD8_MARK, AB_AD9_MARK, + AB_AD10_MARK, AB_AD11_MARK, AB_AD12_MARK, AB_AD13_MARK, + AB_AD14_MARK, AB_AD15_MARK, AB_A17_MARK, AB_A18_MARK, + AB_A19_MARK, AB_A21_MARK, AB_A22_MARK, AB_A23_MARK, + AB_A24_MARK, AB_A25_MARK, AB_A26_MARK, AB_A27_MARK, + AB_A28_MARK, AB_BEN0_MARK, AB_BEN1_MARK, + DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK, + DTV_DATA_A_MARK, + SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK, + SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, + SDI2_DATA3_MARK, + CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK, + CF_IOWRB_MARK, CF_IORDY_MARK, CF_RESET_MARK, + CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK, + CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK, + CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK, + CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK, + CF_A00_MARK, CF_A01_MARK, CF_A02_MARK, + CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK, CF_CDB2_MARK, + USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK, + USI5_CS0_A_MARK, USI5_CS1_A_MARK, USI5_CS2_A_MARK, + + /* CHG_PINSEL_USI */ + USI0_CS3_MARK, USI0_CS4_MARK, USI0_CS5_MARK, + USI0_CS6_MARK, + USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK, + USI2_CS0_MARK, USI2_CS1_MARK, USI2_CS2_MARK, + USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK, + USI3_CS0_MARK, + USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK, + USI4_CS0_MARK, USI4_CS1_MARK, + PWM0_MARK, PWM1_MARK, + DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK, + DTV_DATA_B_MARK, + + /* CHG_PINSEL_HSI */ + USI5_CLK_B_MARK, USI5_DO_B_MARK, USI5_CS0_B_MARK, USI5_CS1_B_MARK, + USI5_CS2_B_MARK, USI5_CS3_B_MARK, USI5_CS4_B_MARK, USI5_DI_B_MARK, + + /* CHG_PINSEL_UART */ + UART1_CTSB_MARK, UART1_RTSB_MARK, + UART2_RX_MARK, UART2_TX_MARK, + + PINMUX_MARK_END, +}; + +/* Pin numbers for pins without a corresponding GPIO port number are computed + * from the row and column numbers with a 1000 offset to avoid collisions with + * GPIO port numbers. */ +#define PIN_NUMBER(row, col) (1000+((row)-1)*23+(col)-1) + +/* Expand to a list of sh_pfc_pin entries (named PORT#). + * NOTE: No config are recorded since the driver do not handle pinconf. */ +#define __PIN_CFG(pn, pfx, sfx) SH_PFC_PIN_CFG(pfx, 0) +#define PINMUX_EMEV_GPIO_ALL() CPU_ALL_PORT(__PIN_CFG, , unused) + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_EMEV_GPIO_ALL(), + + /* Pins not associated with a GPIO port */ + SH_PFC_PIN_NAMED(2, 14, B14), + SH_PFC_PIN_NAMED(2, 15, B15), + SH_PFC_PIN_NAMED(2, 16, B16), + SH_PFC_PIN_NAMED(2, 17, B17), + SH_PFC_PIN_NAMED(3, 14, C14), + SH_PFC_PIN_NAMED(3, 15, C15), + SH_PFC_PIN_NAMED(3, 16, C16), + SH_PFC_PIN_NAMED(3, 17, C17), + SH_PFC_PIN_NAMED(4, 14, D14), + SH_PFC_PIN_NAMED(4, 15, D15), + SH_PFC_PIN_NAMED(4, 16, D16), + SH_PFC_PIN_NAMED(4, 17, D17), +}; + +/* Expand to a list of name_DATA, name_FN marks */ +#define __PORT_DATA(pn, pfx, sfx) PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN) +#define PINMUX_EMEV_DATA_ALL() CPU_ALL_PORT(__PORT_DATA, , unused) + +static const u16 pinmux_data[] = { + PINMUX_EMEV_DATA_ALL(), /* PINMUX_DATA(PORTN_DATA, PORTN_FN), */ + + /* GPSR0 */ + /* V9 */ + PINMUX_DATA(JT_SEL_MARK, FN_JT_SEL), + /* U9 */ + PINMUX_DATA(ERR_RST_REQB_MARK, FN_ERR_RST_REQB), + /* V8 */ + PINMUX_DATA(REF_CLKO_MARK, FN_REF_CLKO), + /* U8 */ + PINMUX_DATA(EXT_CLKI_MARK, FN_EXT_CLKI), + /* B22*/ + PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, LCD3_PXCLK, SEL_LCD3_1_0_00), + PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, YUV3_CLK_O, SEL_LCD3_1_0_01), + /* C21 */ + PINMUX_DATA(LCD3_PXCLKB_MARK, FN_LCD3_PXCLKB), + /* A21 */ + PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, LCD3_CLK_I, SEL_LCD3_1_0_00), + PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, YUV3_CLK_I, SEL_LCD3_1_0_01), + /* B21 */ + PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, LCD3_HS, SEL_LCD3_1_0_00), + PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, YUV3_HS, SEL_LCD3_1_0_01), + /* C20 */ + PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, LCD3_VS, SEL_LCD3_1_0_00), + PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, YUV3_VS, SEL_LCD3_1_0_01), + /* D19 */ + PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, LCD3_DE, SEL_LCD3_1_0_00), + PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, YUV3_DE, SEL_LCD3_1_0_01), + + /* GPSR1 */ + /* A20 */ + PINMUX_DATA(LCD3_R0_MARK, FN_LCD3_R0), + /* B20 */ + PINMUX_DATA(LCD3_R1_MARK, FN_LCD3_R1), + /* A19 */ + PINMUX_DATA(LCD3_R2_MARK, FN_LCD3_R2), + /* B19 */ + PINMUX_DATA(LCD3_R3_MARK, FN_LCD3_R3), + /* C19 */ + PINMUX_DATA(LCD3_R4_MARK, FN_LCD3_R4), + /* B18 */ + PINMUX_DATA(LCD3_R5_MARK, FN_LCD3_R5), + /* C18 */ + PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, LCD3_R6, SEL_LCD3_9_8_00), + PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, TP33_CLK, SEL_LCD3_9_8_10), + /* D18 */ + PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, LCD3_R7, SEL_LCD3_9_8_00), + PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, TP33_CTRL, SEL_LCD3_9_8_10), + /* A18 */ + PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, LCD3_G0, SEL_LCD3_11_10_00), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, YUV3_D0, SEL_LCD3_11_10_01), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, TP33_DATA0, SEL_LCD3_11_10_10), + /* A17 */ + PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, LCD3_G1, SEL_LCD3_11_10_00), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, YUV3_D1, SEL_LCD3_11_10_01), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, TP33_DATA1, SEL_LCD3_11_10_10), + /* B17 */ + PINMUX_DATA(LCD3_G2_MARK, FN_SEL_LCD3_11_10_00), + PINMUX_DATA(YUV3_D2_MARK, FN_SEL_LCD3_11_10_01), + PINMUX_DATA(TP33_DATA2_MARK, FN_SEL_LCD3_11_10_10), + /* C17 */ + PINMUX_DATA(LCD3_G3_MARK, FN_SEL_LCD3_11_10_00), + PINMUX_DATA(YUV3_D3_MARK, FN_SEL_LCD3_11_10_01), + PINMUX_DATA(TP33_DATA3_MARK, FN_SEL_LCD3_11_10_10), + /* D17 */ + PINMUX_DATA(LCD3_G4_MARK, FN_SEL_LCD3_11_10_00), + PINMUX_DATA(YUV3_D4_MARK, FN_SEL_LCD3_11_10_01), + PINMUX_DATA(TP33_DATA4_MARK, FN_SEL_LCD3_11_10_10), + /* B16 */ + PINMUX_DATA(LCD3_G5_MARK, FN_SEL_LCD3_11_10_00), + PINMUX_DATA(YUV3_D5_MARK, FN_SEL_LCD3_11_10_01), + PINMUX_DATA(TP33_DATA5_MARK, FN_SEL_LCD3_11_10_10), + /* C16 */ + PINMUX_DATA(LCD3_G6_MARK, FN_SEL_LCD3_11_10_00), + PINMUX_DATA(YUV3_D6_MARK, FN_SEL_LCD3_11_10_01), + PINMUX_DATA(TP33_DATA6_MARK, FN_SEL_LCD3_11_10_10), + /* D16 */ + PINMUX_DATA(LCD3_G7_MARK, FN_SEL_LCD3_11_10_00), + PINMUX_DATA(YUV3_D7_MARK, FN_SEL_LCD3_11_10_01), + PINMUX_DATA(TP33_DATA7_MARK, FN_SEL_LCD3_11_10_10), + /* A16 */ + PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, LCD3_B0, SEL_LCD3_11_10_00), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, YUV3_D8, SEL_LCD3_11_10_01), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, TP33_DATA8, SEL_LCD3_11_10_10), + /* A15 */ + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B1, SEL_LCD3_11_10_00), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D9, SEL_LCD3_11_10_01), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA9, SEL_LCD3_11_10_10), + /* B15 */ + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B2, SEL_LCD3_11_10_00), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D10, SEL_LCD3_11_10_01), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA10, SEL_LCD3_11_10_10), + /* C15 */ + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B3, SEL_LCD3_11_10_00), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D11, SEL_LCD3_11_10_01), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA11, SEL_LCD3_11_10_10), + /* D15 */ + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B4, SEL_LCD3_11_10_00), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D12, SEL_LCD3_11_10_01), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA12, SEL_LCD3_11_10_10), + /* B14 */ + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B5, SEL_LCD3_11_10_00), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D13, SEL_LCD3_11_10_01), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA13, SEL_LCD3_11_10_10), + /* C14 */ + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B6, SEL_LCD3_11_10_00), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D14, SEL_LCD3_11_10_01), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA14, SEL_LCD3_11_10_10), + /* D14 */ + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B7, SEL_LCD3_11_10_00), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D15, SEL_LCD3_11_10_01), + PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA15, SEL_LCD3_11_10_10), + /* AA9 */ + PINMUX_DATA(IIC0_SCL_MARK, FN_IIC0_SCL), + /* AA8 */ + PINMUX_DATA(IIC0_SDA_MARK, FN_IIC0_SDA), + /* Y9 */ + PINMUX_IPSR_NOFN(IIC_1_0_PORT46, IIC1_SCL, SEL_IIC_1_0_00), + PINMUX_IPSR_NOFN(IIC_1_0_PORT46, UART3_RX, SEL_IIC_1_0_01), + /* Y8 */ + PINMUX_IPSR_NOFN(IIC_1_0_PORT47, IIC1_SDA, SEL_IIC_1_0_00), + PINMUX_IPSR_NOFN(IIC_1_0_PORT47, UART3_TX, SEL_IIC_1_0_01), + /* AC19 */ + PINMUX_DATA(SD_CKI_MARK, FN_SD_CKI), + /* AB18 */ + PINMUX_DATA(SDI0_CKO_MARK, FN_SDI0_CKO), + /* AC18 */ + PINMUX_DATA(SDI0_CKI_MARK, FN_SDI0_CKI), + /* Y12 */ + PINMUX_DATA(SDI0_CMD_MARK, FN_SDI0_CMD), + /* AA13 */ + PINMUX_DATA(SDI0_DATA0_MARK, FN_SDI0_DATA0), + /* Y13 */ + PINMUX_DATA(SDI0_DATA1_MARK, FN_SDI0_DATA1), + /* AA14 */ + PINMUX_DATA(SDI0_DATA2_MARK, FN_SDI0_DATA2), + /* Y14 */ + PINMUX_DATA(SDI0_DATA3_MARK, FN_SDI0_DATA3), + /* AA15 */ + PINMUX_DATA(SDI0_DATA4_MARK, FN_SDI0_DATA4), + /* Y15 */ + PINMUX_DATA(SDI0_DATA5_MARK, FN_SDI0_DATA5), + /* AA16 */ + PINMUX_DATA(SDI0_DATA6_MARK, FN_SDI0_DATA6), + /* Y16 */ + PINMUX_DATA(SDI0_DATA7_MARK, FN_SDI0_DATA7), + /* AB22 */ + PINMUX_DATA(SDI1_CKO_MARK, FN_SDI1_CKO), + /* AA23 */ + PINMUX_DATA(SDI1_CKI_MARK, FN_SDI1_CKI), + /* AC21 */ + PINMUX_DATA(SDI1_CMD_MARK, FN_SDI1_CMD), + + /* GPSR2 */ + /* AB21 */ + PINMUX_DATA(SDI1_DATA0_MARK, FN_SDI1_DATA0), + /* AB20 */ + PINMUX_DATA(SDI1_DATA1_MARK, FN_SDI1_DATA1), + /* AB19 */ + PINMUX_DATA(SDI1_DATA2_MARK, FN_SDI1_DATA2), + /* AA19 */ + PINMUX_DATA(SDI1_DATA3_MARK, FN_SDI1_DATA3), + /* J23 */ + PINMUX_DATA(AB_CLK_MARK, FN_AB_CLK), + /* D21 */ + PINMUX_DATA(AB_CSB0_MARK, FN_AB_CSB0), + /* E21 */ + PINMUX_DATA(AB_CSB1_MARK, FN_AB_CSB1), + /* F20 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT71, AB_CSB2, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT71, CF_CSB0, SEL_AB_1_0_10), + /* G20 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT72, AB_CSB3, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT72, CF_CSB1, SEL_AB_1_0_10), + /* J20 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT73, AB_RDB, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT73, CF_IORDB, SEL_AB_1_0_10), + /* H20 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT74, AB_WRB, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT74, CF_IOWRB, SEL_AB_1_0_10), + /* L20 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT75, AB_WAIT, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT75, CF_IORDY, SEL_AB_1_0_10), + /* K20 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT76, AB_ADV, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT76, CF_RESET, SEL_AB_1_0_10), + /* C23 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT77, AB_AD0, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT77, CF_D00, SEL_AB_1_0_10), + /* C22 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT78, AB_AD1, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT78, CF_D01, SEL_AB_1_0_10), + /* D23 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT79, AB_AD2, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT79, CF_D02, SEL_AB_1_0_10), + /* D22 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT80, AB_AD3, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT80, CF_D03, SEL_AB_1_0_10), + /* E23 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT81, AB_AD4, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT81, CF_D04, SEL_AB_1_0_10), + /* E22 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT82, AB_AD5, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT82, CF_D05, SEL_AB_1_0_10), + /* F23 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT83, AB_AD6, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT83, CF_D06, SEL_AB_1_0_10), + /* F22 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT84, AB_AD7, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT84, CF_D07, SEL_AB_1_0_10), + /* F21 */ + PINMUX_IPSR_NOFN(AB_3_2_PORT85, AB_AD8, SEL_AB_3_2_00), + PINMUX_IPSR_NOFN(AB_3_2_PORT85, DTV_BCLK_A, SEL_AB_3_2_01), + PINMUX_IPSR_NOFN(AB_3_2_PORT85, CF_D08, SEL_AB_3_2_10), + PINMUX_IPSR_NOFN(AB_3_2_PORT85, USI5_CLK_A, SEL_AB_3_2_11), + /* G23 */ + PINMUX_IPSR_NOFN(AB_3_2_PORT86, AB_AD9, SEL_AB_3_2_00), + PINMUX_IPSR_NOFN(AB_3_2_PORT86, DTV_PSYNC_A, SEL_AB_3_2_01), + PINMUX_IPSR_NOFN(AB_3_2_PORT86, CF_D09, SEL_AB_3_2_10), + PINMUX_IPSR_NOFN(AB_3_2_PORT86, USI5_DI_A, SEL_AB_3_2_11), + /* G22 */ + PINMUX_IPSR_NOFN(AB_3_2_PORT87, AB_AD10, SEL_AB_3_2_00), + PINMUX_IPSR_NOFN(AB_3_2_PORT87, DTV_VALID_A, SEL_AB_3_2_01), + PINMUX_IPSR_NOFN(AB_3_2_PORT87, CF_D10, SEL_AB_3_2_10), + PINMUX_IPSR_NOFN(AB_3_2_PORT87, USI5_DO_A, SEL_AB_3_2_11), + /* G21 */ + PINMUX_IPSR_NOFN(AB_3_2_PORT88, AB_AD11, SEL_AB_3_2_00), + PINMUX_IPSR_NOFN(AB_3_2_PORT88, DTV_DATA_A, SEL_AB_3_2_01), + PINMUX_IPSR_NOFN(AB_3_2_PORT88, CF_D11, SEL_AB_3_2_10), + PINMUX_IPSR_NOFN(AB_3_2_PORT88, USI5_CS0_A, SEL_AB_3_2_11), + /* H23 */ + PINMUX_IPSR_NOFN(AB_5_4_PORT89, AB_AD12, SEL_AB_5_4_00), + PINMUX_IPSR_NOFN(AB_5_4_PORT89, SDI2_DATA0, SEL_AB_5_4_01), + PINMUX_IPSR_NOFN(AB_5_4_PORT89, CF_D12, SEL_AB_5_4_10), + PINMUX_IPSR_NOFN(AB_5_4_PORT89, USI5_CS1_A, SEL_AB_5_4_11), + /* H22 */ + PINMUX_IPSR_NOFN(AB_5_4_PORT90, AB_AD13, SEL_AB_5_4_00), + PINMUX_IPSR_NOFN(AB_5_4_PORT90, SDI2_DATA1, SEL_AB_5_4_01), + PINMUX_IPSR_NOFN(AB_5_4_PORT90, CF_D13, SEL_AB_5_4_10), + PINMUX_IPSR_NOFN(AB_5_4_PORT90, USI5_CS2_A, SEL_AB_5_4_11), + /* H21 */ + PINMUX_IPSR_NOFN(AB_7_6_PORT91, AB_AD14, SEL_AB_7_6_00), + PINMUX_IPSR_NOFN(AB_7_6_PORT91, SDI2_DATA2, SEL_AB_7_6_01), + PINMUX_IPSR_NOFN(AB_7_6_PORT91, CF_D14, SEL_AB_7_6_10), + /* J22 */ + PINMUX_IPSR_NOFN(AB_7_6_PORT92, AB_AD15, SEL_AB_7_6_00), + PINMUX_IPSR_NOFN(AB_7_6_PORT92, SDI2_DATA3, SEL_AB_7_6_01), + PINMUX_IPSR_NOFN(AB_7_6_PORT92, CF_D15, SEL_AB_7_6_10), + /* J21 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT93, AB_A17, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT93, CF_A00, SEL_AB_1_0_10), + /* K21 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT94, AB_A18, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT94, CF_A01, SEL_AB_1_0_10), + /* L21 */ + PINMUX_IPSR_NOFN(AB_1_0_PORT95, AB_A19, SEL_AB_1_0_00), + PINMUX_IPSR_NOFN(AB_1_0_PORT95, CF_A02, SEL_AB_1_0_10), + + /* GPSR3 */ + /* M21 */ + PINMUX_DATA(AB_A20_MARK, FN_AB_A20), + /* N21 */ + PINMUX_IPSR_NOFN(AB_9_8_PORT97, AB_A21, SEL_AB_9_8_00), + PINMUX_IPSR_NOFN(AB_9_8_PORT97, SDI2_CKO, SEL_AB_9_8_01), + PINMUX_IPSR_NOFN(AB_9_8_PORT97, CF_INTRQ, SEL_AB_9_8_10), + /* M20 */ + PINMUX_IPSR_NOFN(AB_9_8_PORT98, AB_A22, SEL_AB_9_8_00), + PINMUX_IPSR_NOFN(AB_9_8_PORT98, SDI2_CKI, SEL_AB_9_8_01), + /* N20 */ + PINMUX_IPSR_NOFN(AB_9_8_PORT99, AB_A23, SEL_AB_9_8_00), + PINMUX_IPSR_NOFN(AB_9_8_PORT99, SDI2_CMD, SEL_AB_9_8_01), + /* L18 */ + PINMUX_IPSR_NOFN(AB_11_10_PORT100, AB_A24, SEL_AB_11_10_00), + PINMUX_IPSR_NOFN(AB_11_10_PORT100, CF_INPACKB, SEL_AB_11_10_10), + /* M18 */ + PINMUX_IPSR_NOFN(AB_11_10_PORT101, AB_A25, SEL_AB_11_10_00), + PINMUX_IPSR_NOFN(AB_11_10_PORT101, CF_CDB1, SEL_AB_11_10_10), + /* N18 */ + PINMUX_IPSR_NOFN(AB_11_10_PORT102, AB_A26, SEL_AB_11_10_00), + PINMUX_IPSR_NOFN(AB_11_10_PORT102, CF_CDB2, SEL_AB_11_10_10), + /* L17 */ + PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_A27, SEL_AB_13_12_00), + PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_BEN0, SEL_AB_13_12_10), + /* M17 */ + PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_A28, SEL_AB_13_12_00), + PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_BEN1, SEL_AB_13_12_10), + /* B8 */ + PINMUX_DATA(USI0_CS1_MARK, FN_USI0_CS1), + /* B9 */ + PINMUX_DATA(USI0_CS2_MARK, FN_USI0_CS2), + /* C10 */ + PINMUX_DATA(USI1_DI_MARK, FN_USI1_DI), + /* D10 */ + PINMUX_DATA(USI1_DO_MARK, FN_USI1_DO), + /* AB5 */ + PINMUX_IPSR_NOFN(USI_1_0_PORT109, USI2_CLK, SEL_USI_1_0_00), + PINMUX_IPSR_NOFN(USI_1_0_PORT109, DTV_BCLK_B, SEL_USI_1_0_01), + /* AA6 */ + PINMUX_IPSR_NOFN(USI_1_0_PORT110, USI2_DI, SEL_USI_1_0_00), + PINMUX_IPSR_NOFN(USI_1_0_PORT110, DTV_PSYNC_B, SEL_USI_1_0_01), + /* AA5 */ + PINMUX_IPSR_NOFN(USI_1_0_PORT111, USI2_DO, SEL_USI_1_0_00), + PINMUX_IPSR_NOFN(USI_1_0_PORT111, DTV_VALID_B, SEL_USI_1_0_01), + /* Y7 */ + PINMUX_IPSR_NOFN(USI_1_0_PORT112, USI2_CS0, SEL_USI_1_0_00), + PINMUX_IPSR_NOFN(USI_1_0_PORT112, DTV_DATA_B, SEL_USI_1_0_01), + /* AA7 */ + PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI2_CS1, SEL_USI_3_2_00), + PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI4_CS0, SEL_USI_3_2_01), + /* Y6 */ + PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI2_CS2, SEL_USI_3_2_00), + PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI4_CS1, SEL_USI_3_2_01), + /* AC5 */ + PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI3_CLK, SEL_USI_5_4_00), + PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI0_CS3, SEL_USI_5_4_01), + /* AC4 */ + PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI3_DI, SEL_USI_5_4_00), + PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI0_CS4, SEL_USI_5_4_01), + /* AC3 */ + PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI3_DO, SEL_USI_5_4_00), + PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI0_CS5, SEL_USI_5_4_01), + /* AB4 */ + PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI3_CS0, SEL_USI_5_4_00), + PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI0_CS6, SEL_USI_5_4_01), + /* AB3 */ + PINMUX_IPSR_NOFN(USI_7_6_PORT119, USI4_CLK, SEL_USI_7_6_01), + /* AA4 */ + PINMUX_IPSR_NOFN(USI_9_8_PORT120, PWM0, SEL_USI_9_8_00), + PINMUX_IPSR_NOFN(USI_9_8_PORT120, USI4_DI, SEL_USI_9_8_01), + /* Y5 */ + PINMUX_IPSR_NOFN(USI_9_8_PORT121, PWM1, SEL_USI_9_8_00), + PINMUX_IPSR_NOFN(USI_9_8_PORT121, USI4_DO, SEL_USI_9_8_01), + /* V20 */ + PINMUX_DATA(NTSC_CLK_MARK, FN_NTSC_CLK), + /* P20 */ + PINMUX_DATA(NTSC_DATA0_MARK, FN_NTSC_DATA0), + /* P18 */ + PINMUX_DATA(NTSC_DATA1_MARK, FN_NTSC_DATA1), + /* R20 */ + PINMUX_DATA(NTSC_DATA2_MARK, FN_NTSC_DATA2), + /* R18 */ + PINMUX_DATA(NTSC_DATA3_MARK, FN_NTSC_DATA3), + /* T20 */ + PINMUX_DATA(NTSC_DATA4_MARK, FN_NTSC_DATA4), + + /* GPRS3 */ + /* T18 */ + PINMUX_DATA(NTSC_DATA5_MARK, FN_NTSC_DATA5), + /* U20 */ + PINMUX_DATA(NTSC_DATA6_MARK, FN_NTSC_DATA6), + /* U18 */ + PINMUX_DATA(NTSC_DATA7_MARK, FN_NTSC_DATA7), + /* W23 */ + PINMUX_DATA(CAM_CLKO_MARK, FN_CAM_CLKO), + /* Y23 */ + PINMUX_DATA(CAM_CLKI_MARK, FN_CAM_CLKI), + /* W22 */ + PINMUX_DATA(CAM_VS_MARK, FN_CAM_VS), + /* V21 */ + PINMUX_DATA(CAM_HS_MARK, FN_CAM_HS), + /* T21 */ + PINMUX_DATA(CAM_YUV0_MARK, FN_CAM_YUV0), + /* T22 */ + PINMUX_DATA(CAM_YUV1_MARK, FN_CAM_YUV1), + /* T23 */ + PINMUX_DATA(CAM_YUV2_MARK, FN_CAM_YUV2), + /* U21 */ + PINMUX_DATA(CAM_YUV3_MARK, FN_CAM_YUV3), + /* U22 */ + PINMUX_DATA(CAM_YUV4_MARK, FN_CAM_YUV4), + /* U23 */ + PINMUX_DATA(CAM_YUV5_MARK, FN_CAM_YUV5), + /* V22 */ + PINMUX_DATA(CAM_YUV6_MARK, FN_CAM_YUV6), + /* V23 */ + PINMUX_DATA(CAM_YUV7_MARK, FN_CAM_YUV7), + /* K22 */ + PINMUX_IPSR_NOFN(HSI_1_0_PORT143, USI5_CLK_B, SEL_HSI_1_0_01), + /* K23 */ + PINMUX_IPSR_NOFN(HSI_1_0_PORT144, USI5_DO_B, SEL_HSI_1_0_01), + /* L23 */ + PINMUX_IPSR_NOFN(HSI_1_0_PORT145, USI5_CS0_B, SEL_HSI_1_0_01), + /* L22 */ + PINMUX_IPSR_NOFN(HSI_1_0_PORT146, USI5_CS1_B, SEL_HSI_1_0_01), + /* N22 */ + PINMUX_IPSR_NOFN(HSI_1_0_PORT147, USI5_CS2_B, SEL_HSI_1_0_01), + /* N23 */ + PINMUX_IPSR_NOFN(HSI_1_0_PORT148, USI5_CS3_B, SEL_HSI_1_0_01), + /* M23 */ + PINMUX_IPSR_NOFN(HSI_1_0_PORT149, USI5_CS4_B, SEL_HSI_1_0_01), + /* M22 */ + PINMUX_IPSR_NOFN(HSI_1_0_PORT150, USI5_DI_B, SEL_HSI_1_0_01), + /* D13 */ + PINMUX_DATA(JT_TDO_MARK, FN_JT_TDO), + /* F13 */ + PINMUX_DATA(JT_TDOEN_MARK, FN_JT_TDOEN), + /* AA12 */ + PINMUX_DATA(USB_VBUS_MARK, FN_USB_VBUS), + /* A12 */ + PINMUX_DATA(LOWPWR_MARK, FN_LOWPWR), + /* Y11 */ + PINMUX_DATA(UART1_RX_MARK, FN_UART1_RX), + /* Y10 */ + PINMUX_DATA(UART1_TX_MARK, FN_UART1_TX), + /* AA10 */ + PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART1_CTSB, SEL_UART_1_0_00), + PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART2_RX, SEL_UART_1_0_01), + /* AB10 */ + PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART1_RTSB, SEL_UART_1_0_00), + PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART2_TX, SEL_UART_1_0_01), +}; + + +#define EMEV_MUX_PIN(name, pin, mark) \ + static const unsigned int name##_pins[] = { pin }; \ + static const unsigned int name##_mux[] = { mark##_MARK } + +/* = [ System ] =========== */ +EMEV_MUX_PIN(err_rst_reqb, 3, ERR_RST_REQB); +EMEV_MUX_PIN(ref_clko, 4, REF_CLKO); +EMEV_MUX_PIN(ext_clki, 5, EXT_CLKI); +EMEV_MUX_PIN(lowpwr, 154, LOWPWR); + +/* = [ External Memory] === */ +static const unsigned int ab_main_pins[] = { + /* AB_RDB, AB_WRB */ + 73, 74, + /* AB_AD[0:15] */ + 77, 78, 79, 80, + 81, 82, 83, 84, + 85, 86, 87, 88, + 89, 90, 91, 92, +}; +static const unsigned int ab_main_mux[] = { + AB_RDB_MARK, AB_WRB_MARK, + AB_AD0_MARK, AB_AD1_MARK, AB_AD2_MARK, AB_AD3_MARK, + AB_AD4_MARK, AB_AD5_MARK, AB_AD6_MARK, AB_AD7_MARK, + AB_AD8_MARK, AB_AD9_MARK, AB_AD10_MARK, AB_AD11_MARK, + AB_AD12_MARK, AB_AD13_MARK, AB_AD14_MARK, AB_AD15_MARK, +}; + +EMEV_MUX_PIN(ab_clk, 68, AB_CLK); +EMEV_MUX_PIN(ab_csb0, 69, AB_CSB0); +EMEV_MUX_PIN(ab_csb1, 70, AB_CSB1); +EMEV_MUX_PIN(ab_csb2, 71, AB_CSB2); +EMEV_MUX_PIN(ab_csb3, 72, AB_CSB3); +EMEV_MUX_PIN(ab_wait, 75, AB_WAIT); +EMEV_MUX_PIN(ab_adv, 76, AB_ADV); +EMEV_MUX_PIN(ab_a17, 93, AB_A17); +EMEV_MUX_PIN(ab_a18, 94, AB_A18); +EMEV_MUX_PIN(ab_a19, 95, AB_A19); +EMEV_MUX_PIN(ab_a20, 96, AB_A20); +EMEV_MUX_PIN(ab_a21, 97, AB_A21); +EMEV_MUX_PIN(ab_a22, 98, AB_A22); +EMEV_MUX_PIN(ab_a23, 99, AB_A23); +EMEV_MUX_PIN(ab_a24, 100, AB_A24); +EMEV_MUX_PIN(ab_a25, 101, AB_A25); +EMEV_MUX_PIN(ab_a26, 102, AB_A26); +EMEV_MUX_PIN(ab_a27, 103, AB_A27); +EMEV_MUX_PIN(ab_a28, 104, AB_A28); +EMEV_MUX_PIN(ab_ben0, 103, AB_BEN0); +EMEV_MUX_PIN(ab_ben1, 104, AB_BEN1); + +/* = [ CAM ] ============== */ +EMEV_MUX_PIN(cam_clko, 131, CAM_CLKO); +static const unsigned int cam_pins[] = { + /* CLKI, VS, HS */ + 132, 133, 134, + /* CAM_YUV[0:7] */ + 135, 136, 137, 138, + 139, 140, 141, 142, +}; +static const unsigned int cam_mux[] = { + CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK, + CAM_YUV0_MARK, CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK, + CAM_YUV4_MARK, CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK, +}; + +/* = [ CF ] -============== */ +static const unsigned int cf_ctrl_pins[] = { + /* CSB0, CSB1, IORDB, IOWRB, IORDY, RESET, + * A00, A01, A02, INTRQ, INPACKB, CDB1, CDB2 */ + 71, 72, 73, 74, + 75, 76, 93, 94, + 95, 97, 100, 101, + 102, +}; +static const unsigned int cf_ctrl_mux[] = { + CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK, CF_IOWRB_MARK, + CF_IORDY_MARK, CF_RESET_MARK, CF_A00_MARK, CF_A01_MARK, + CF_A02_MARK, CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK, + CF_CDB2_MARK, +}; + +static const unsigned int cf_data8_pins[] = { + /* CF_D[0:8] */ + 77, 78, 79, 80, + 81, 82, 83, 84, +}; +static const unsigned int cf_data8_mux[] = { + CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK, + CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK, +}; +static const unsigned int cf_data16_pins[] = { + /* CF_D[0:15] */ + 77, 78, 79, 80, + 81, 82, 83, 84, + 85, 86, 87, 88, + 89, 90, 91, 92, +}; +static const unsigned int cf_data16_mux[] = { + CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK, + CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK, + CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK, + CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK, +}; + +/* = [ DTV ] ============== */ +static const unsigned int dtv_a_pins[] = { + /* BCLK, PSYNC, VALID, DATA */ + 85, 86, 87, 88, +}; +static const unsigned int dtv_a_mux[] = { + DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK, DTV_DATA_A_MARK, +}; + +static const unsigned int dtv_b_pins[] = { + /* BCLK, PSYNC, VALID, DATA */ + 109, 110, 111, 112, +}; +static const unsigned int dtv_b_mux[] = { + DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK, DTV_DATA_B_MARK, +}; + +/* = [ IIC0 ] ============= */ +static const unsigned int iic0_pins[] = { + /* SCL, SDA */ + 44, 45, +}; +static const unsigned int iic0_mux[] = { + IIC0_SCL_MARK, IIC0_SDA_MARK, +}; + +/* = [ IIC1 ] ============= */ +static const unsigned int iic1_pins[] = { + /* SCL, SDA */ + 46, 47, +}; +static const unsigned int iic1_mux[] = { + IIC1_SCL_MARK, IIC1_SDA_MARK, +}; + +/* = [ JTAG ] ============= */ +static const unsigned int jtag_pins[] = { + /* SEL, TDO, TDOEN */ + 2, 151, 152, +}; +static const unsigned int jtag_mux[] = { + JT_SEL_MARK, JT_TDO_MARK, JT_TDOEN_MARK, +}; + +/* = [ LCD/YUV ] ========== */ +EMEV_MUX_PIN(lcd3_pxclk, 18, LCD3_PXCLK); +EMEV_MUX_PIN(lcd3_pxclkb, 19, LCD3_PXCLKB); +EMEV_MUX_PIN(lcd3_clk_i, 20, LCD3_CLK_I); + +static const unsigned int lcd3_sync_pins[] = { + /* HS, VS, DE */ + 21, 22, 23, +}; +static const unsigned int lcd3_sync_mux[] = { + LCD3_HS_MARK, LCD3_VS_MARK, LCD3_DE_MARK, +}; + +static const unsigned int lcd3_rgb888_pins[] = { + /* R[0:7], G[0:7], B[0:7] */ + 32, 33, 34, 35, + 36, 37, 38, 39, + 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17), + PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16), + PIN_NUMBER(4, 16), + 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15), + PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14), + PIN_NUMBER(4, 14) +}; +static const unsigned int lcd3_rgb888_mux[] = { + LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK, + LCD3_R4_MARK, LCD3_R5_MARK, LCD3_R6_MARK, LCD3_R7_MARK, + LCD3_G0_MARK, LCD3_G1_MARK, LCD3_G2_MARK, LCD3_G3_MARK, + LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK, LCD3_G7_MARK, + LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK, + LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK, +}; + +EMEV_MUX_PIN(yuv3_clk_i, 20, YUV3_CLK_I); +static const unsigned int yuv3_pins[] = { + /* CLK_O, HS, VS, DE */ + 18, 21, 22, 23, + /* YUV3_D[0:15] */ + 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17), + PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16), + PIN_NUMBER(4, 16), + 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15), + PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14), + PIN_NUMBER(4, 14), +}; +static const unsigned int yuv3_mux[] = { + YUV3_CLK_O_MARK, YUV3_HS_MARK, YUV3_VS_MARK, YUV3_DE_MARK, + YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK, + YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK, + YUV3_D8_MARK, YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK, + YUV3_D12_MARK, YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK, +}; + +/* = [ NTSC ] ============= */ +EMEV_MUX_PIN(ntsc_clk, 122, NTSC_CLK); +static const unsigned int ntsc_data_pins[] = { + /* NTSC_DATA[0:7] */ + 123, 124, 125, 126, + 127, 128, 129, 130, +}; +static const unsigned int ntsc_data_mux[] = { + NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK, NTSC_DATA3_MARK, + NTSC_DATA4_MARK, NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK, +}; + +/* = [ PWM0 ] ============= */ +EMEV_MUX_PIN(pwm0, 120, PWM0); + +/* = [ PWM1 ] ============= */ +EMEV_MUX_PIN(pwm1, 121, PWM1); + +/* = [ SD ] =============== */ +EMEV_MUX_PIN(sd_cki, 48, SD_CKI); + +/* = [ SDIO0 ] ============ */ +static const unsigned int sdi0_ctrl_pins[] = { + /* CKO, CKI, CMD */ + 50, 51, 52, +}; +static const unsigned int sdi0_ctrl_mux[] = { + SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK, +}; + +static const unsigned int sdi0_data1_pins[] = { + /* SDI0_DATA[0] */ + 53, +}; +static const unsigned int sdi0_data1_mux[] = { + SDI0_DATA0_MARK, +}; +static const unsigned int sdi0_data4_pins[] = { + /* SDI0_DATA[0:3] */ + 53, 54, 55, 56, +}; +static const unsigned int sdi0_data4_mux[] = { + SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK, +}; +static const unsigned int sdi0_data8_pins[] = { + /* SDI0_DATA[0:7] */ + 53, 54, 55, 56, + 57, 58, 59, 60 +}; +static const unsigned int sdi0_data8_mux[] = { + SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK, + SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK, +}; + +/* = [ SDIO1 ] ============ */ +static const unsigned int sdi1_ctrl_pins[] = { + /* CKO, CKI, CMD */ + 61, 62, 63, +}; +static const unsigned int sdi1_ctrl_mux[] = { + SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK, +}; + +static const unsigned int sdi1_data1_pins[] = { + /* SDI1_DATA[0] */ + 64, +}; +static const unsigned int sdi1_data1_mux[] = { + SDI1_DATA0_MARK, +}; +static const unsigned int sdi1_data4_pins[] = { + /* SDI1_DATA[0:3] */ + 64, 65, 66, 67, +}; +static const unsigned int sdi1_data4_mux[] = { + SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK, +}; + +/* = [ SDIO2 ] ============ */ +static const unsigned int sdi2_ctrl_pins[] = { + /* CKO, CKI, CMD */ + 97, 98, 99, +}; +static const unsigned int sdi2_ctrl_mux[] = { + SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK, +}; + +static const unsigned int sdi2_data1_pins[] = { + /* SDI2_DATA[0] */ + 89, +}; +static const unsigned int sdi2_data1_mux[] = { + SDI2_DATA0_MARK, +}; +static const unsigned int sdi2_data4_pins[] = { + /* SDI2_DATA[0:3] */ + 89, 90, 91, 92, +}; +static const unsigned int sdi2_data4_mux[] = { + SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK, +}; + +/* = [ TP33 ] ============= */ +static const unsigned int tp33_pins[] = { + /* CLK, CTRL */ + 38, 39, + /* TP33_DATA[0:15] */ + 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17), + PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16), + PIN_NUMBER(4, 16), + 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15), + PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14), + PIN_NUMBER(4, 14), +}; +static const unsigned int tp33_mux[] = { + TP33_CLK_MARK, TP33_CTRL_MARK, + TP33_DATA0_MARK, TP33_DATA1_MARK, TP33_DATA2_MARK, TP33_DATA3_MARK, + TP33_DATA4_MARK, TP33_DATA5_MARK, TP33_DATA6_MARK, TP33_DATA7_MARK, + TP33_DATA8_MARK, TP33_DATA9_MARK, TP33_DATA10_MARK, TP33_DATA11_MARK, + TP33_DATA12_MARK, TP33_DATA13_MARK, TP33_DATA14_MARK, TP33_DATA15_MARK, +}; + +/* = [ UART1 ] ============ */ +static const unsigned int uart1_data_pins[] = { + /* RX, TX */ + 155, 156, +}; +static const unsigned int uart1_data_mux[] = { + UART1_RX_MARK, UART1_TX_MARK, +}; + +static const unsigned int uart1_ctrl_pins[] = { + /* CTSB, RTSB */ + 157, 158, +}; +static const unsigned int uart1_ctrl_mux[] = { + UART1_CTSB_MARK, UART1_RTSB_MARK, +}; + +/* = [ UART2 ] ============ */ +static const unsigned int uart2_data_pins[] = { + /* RX, TX */ + 157, 158, +}; +static const unsigned int uart2_data_mux[] = { + UART2_RX_MARK, UART2_TX_MARK, +}; + +/* = [ UART3 ] ============ */ +static const unsigned int uart3_data_pins[] = { + /* RX, TX */ + 46, 47, +}; +static const unsigned int uart3_data_mux[] = { + UART3_RX_MARK, UART3_TX_MARK, +}; + +/* = [ USB ] ============== */ +EMEV_MUX_PIN(usb_vbus, 153, USB_VBUS); + +/* = [ USI0 ] ============== */ +EMEV_MUX_PIN(usi0_cs1, 105, USI0_CS1); +EMEV_MUX_PIN(usi0_cs2, 106, USI0_CS2); +EMEV_MUX_PIN(usi0_cs3, 115, USI0_CS3); +EMEV_MUX_PIN(usi0_cs4, 116, USI0_CS4); +EMEV_MUX_PIN(usi0_cs5, 117, USI0_CS5); +EMEV_MUX_PIN(usi0_cs6, 118, USI0_CS6); + +/* = [ USI1 ] ============== */ +static const unsigned int usi1_pins[] = { + /* DI, DO*/ + 107, 108, +}; +static const unsigned int usi1_mux[] = { + USI1_DI_MARK, USI1_DO_MARK, +}; + +/* = [ USI2 ] ============== */ +static const unsigned int usi2_pins[] = { + /* CLK, DI, DO*/ + 109, 110, 111, +}; +static const unsigned int usi2_mux[] = { + USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK, +}; +EMEV_MUX_PIN(usi2_cs0, 112, USI2_CS0); +EMEV_MUX_PIN(usi2_cs1, 113, USI2_CS1); +EMEV_MUX_PIN(usi2_cs2, 114, USI2_CS2); + +/* = [ USI3 ] ============== */ +static const unsigned int usi3_pins[] = { + /* CLK, DI, DO*/ + 115, 116, 117, +}; +static const unsigned int usi3_mux[] = { + USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK, +}; +EMEV_MUX_PIN(usi3_cs0, 118, USI3_CS0); + +/* = [ USI4 ] ============== */ +static const unsigned int usi4_pins[] = { + /* CLK, DI, DO*/ + 119, 120, 121, +}; +static const unsigned int usi4_mux[] = { + USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK, +}; +EMEV_MUX_PIN(usi4_cs0, 113, USI4_CS0); +EMEV_MUX_PIN(usi4_cs1, 114, USI4_CS1); + +/* = [ USI5 ] ============== */ +static const unsigned int usi5_a_pins[] = { + /* CLK, DI, DO*/ + 85, 86, 87, +}; +static const unsigned int usi5_a_mux[] = { + USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK, +}; +EMEV_MUX_PIN(usi5_cs0_a, 88, USI5_CS0_A); +EMEV_MUX_PIN(usi5_cs1_a, 89, USI5_CS1_A); +EMEV_MUX_PIN(usi5_cs2_a, 90, USI5_CS2_A); + +static const unsigned int usi5_b_pins[] = { + /* CLK, DI, DO*/ + 143, 144, 150, +}; +static const unsigned int usi5_b_mux[] = { + USI5_CLK_B_MARK, USI5_DI_B_MARK, USI5_DO_B_MARK, +}; +EMEV_MUX_PIN(usi5_cs0_b, 145, USI5_CS0_B); +EMEV_MUX_PIN(usi5_cs1_b, 146, USI5_CS1_B); +EMEV_MUX_PIN(usi5_cs2_b, 147, USI5_CS2_B); +EMEV_MUX_PIN(usi5_cs3_b, 148, USI5_CS3_B); +EMEV_MUX_PIN(usi5_cs4_b, 149, USI5_CS4_B); + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(err_rst_reqb), + SH_PFC_PIN_GROUP(ref_clko), + SH_PFC_PIN_GROUP(ext_clki), + SH_PFC_PIN_GROUP(lowpwr), + + SH_PFC_PIN_GROUP(ab_main), + SH_PFC_PIN_GROUP(ab_clk), + SH_PFC_PIN_GROUP(ab_csb0), + SH_PFC_PIN_GROUP(ab_csb1), + SH_PFC_PIN_GROUP(ab_csb2), + SH_PFC_PIN_GROUP(ab_csb3), + SH_PFC_PIN_GROUP(ab_wait), + SH_PFC_PIN_GROUP(ab_adv), + SH_PFC_PIN_GROUP(ab_a17), + SH_PFC_PIN_GROUP(ab_a18), + SH_PFC_PIN_GROUP(ab_a19), + SH_PFC_PIN_GROUP(ab_a20), + SH_PFC_PIN_GROUP(ab_a21), + SH_PFC_PIN_GROUP(ab_a22), + SH_PFC_PIN_GROUP(ab_a23), + SH_PFC_PIN_GROUP(ab_a24), + SH_PFC_PIN_GROUP(ab_a25), + SH_PFC_PIN_GROUP(ab_a26), + SH_PFC_PIN_GROUP(ab_a27), + SH_PFC_PIN_GROUP(ab_a28), + SH_PFC_PIN_GROUP(ab_ben0), + SH_PFC_PIN_GROUP(ab_ben1), + + SH_PFC_PIN_GROUP(cam_clko), + SH_PFC_PIN_GROUP(cam), + + SH_PFC_PIN_GROUP(cf_ctrl), + SH_PFC_PIN_GROUP(cf_data8), + SH_PFC_PIN_GROUP(cf_data16), + + SH_PFC_PIN_GROUP(dtv_a), + SH_PFC_PIN_GROUP(dtv_b), + + SH_PFC_PIN_GROUP(iic0), + + SH_PFC_PIN_GROUP(iic1), + + SH_PFC_PIN_GROUP(jtag), + + SH_PFC_PIN_GROUP(lcd3_pxclk), + SH_PFC_PIN_GROUP(lcd3_pxclkb), + SH_PFC_PIN_GROUP(lcd3_clk_i), + SH_PFC_PIN_GROUP(lcd3_sync), + SH_PFC_PIN_GROUP(lcd3_rgb888), + SH_PFC_PIN_GROUP(yuv3_clk_i), + SH_PFC_PIN_GROUP(yuv3), + + SH_PFC_PIN_GROUP(ntsc_clk), + SH_PFC_PIN_GROUP(ntsc_data), + + SH_PFC_PIN_GROUP(pwm0), + + SH_PFC_PIN_GROUP(pwm1), + + SH_PFC_PIN_GROUP(sd_cki), + + SH_PFC_PIN_GROUP(sdi0_ctrl), + SH_PFC_PIN_GROUP(sdi0_data1), + SH_PFC_PIN_GROUP(sdi0_data4), + SH_PFC_PIN_GROUP(sdi0_data8), + + SH_PFC_PIN_GROUP(sdi1_ctrl), + SH_PFC_PIN_GROUP(sdi1_data1), + SH_PFC_PIN_GROUP(sdi1_data4), + + SH_PFC_PIN_GROUP(sdi2_ctrl), + SH_PFC_PIN_GROUP(sdi2_data1), + SH_PFC_PIN_GROUP(sdi2_data4), + + SH_PFC_PIN_GROUP(tp33), + + SH_PFC_PIN_GROUP(uart1_data), + SH_PFC_PIN_GROUP(uart1_ctrl), + + SH_PFC_PIN_GROUP(uart2_data), + + SH_PFC_PIN_GROUP(uart3_data), + + SH_PFC_PIN_GROUP(usb_vbus), + + SH_PFC_PIN_GROUP(usi0_cs1), + SH_PFC_PIN_GROUP(usi0_cs2), + SH_PFC_PIN_GROUP(usi0_cs3), + SH_PFC_PIN_GROUP(usi0_cs4), + SH_PFC_PIN_GROUP(usi0_cs5), + SH_PFC_PIN_GROUP(usi0_cs6), + + SH_PFC_PIN_GROUP(usi1), + + SH_PFC_PIN_GROUP(usi2), + SH_PFC_PIN_GROUP(usi2_cs0), + SH_PFC_PIN_GROUP(usi2_cs1), + SH_PFC_PIN_GROUP(usi2_cs2), + + SH_PFC_PIN_GROUP(usi3), + SH_PFC_PIN_GROUP(usi3_cs0), + + SH_PFC_PIN_GROUP(usi4), + SH_PFC_PIN_GROUP(usi4_cs0), + SH_PFC_PIN_GROUP(usi4_cs1), + + SH_PFC_PIN_GROUP(usi5_a), + SH_PFC_PIN_GROUP(usi5_cs0_a), + SH_PFC_PIN_GROUP(usi5_cs1_a), + SH_PFC_PIN_GROUP(usi5_cs2_a), + SH_PFC_PIN_GROUP(usi5_b), + SH_PFC_PIN_GROUP(usi5_cs0_b), + SH_PFC_PIN_GROUP(usi5_cs1_b), + SH_PFC_PIN_GROUP(usi5_cs2_b), + SH_PFC_PIN_GROUP(usi5_cs3_b), + SH_PFC_PIN_GROUP(usi5_cs4_b), +}; + +static const char * const ab_groups[] = { + "ab_main", + "ab_clk", + "ab_csb0", + "ab_csb1", + "ab_csb2", + "ab_csb3", + "ab_wait", + "ab_adv", + "ab_a17", + "ab_a18", + "ab_a19", + "ab_a20", + "ab_a21", + "ab_a22", + "ab_a23", + "ab_a24", + "ab_a25", + "ab_a26", + "ab_a27", + "ab_a28", + "ab_ben0", + "ab_ben1", +}; + +static const char * const cam_groups[] = { + "cam_clko", + "cam", +}; + +static const char * const cf_groups[] = { + "cf_ctrl", + "cf_data8", + "cf_data16", +}; + +static const char * const dtv_groups[] = { + "dtv_a", + "dtv_b", +}; + +static const char * const iic0_groups[] = { + "iic0", +}; + +static const char * const iic1_groups[] = { + "iic1", +}; + +static const char * const jtag_groups[] = { + "jtag", +}; + +static const char * const lcd_groups[] = { + "lcd3_pxclk", + "lcd3_pxclkb", + "lcd3_clk_i", + "lcd3_sync", + "lcd3_rgb888", + "yuv3_clk_i", + "yuv3", +}; + +static const char * const ntsc_groups[] = { + "ntsc_clk", + "ntsc_data", +}; + +static const char * const pwm0_groups[] = { + "pwm0", +}; + +static const char * const pwm1_groups[] = { + "pwm1", +}; + +static const char * const sd_groups[] = { + "sd_cki", +}; + +static const char * const sdi0_groups[] = { + "sdi0_ctrl", + "sdi0_data1", + "sdi0_data4", + "sdi0_data8", +}; + +static const char * const sdi1_groups[] = { + "sdi1_ctrl", + "sdi1_data1", + "sdi1_data4", +}; + +static const char * const sdi2_groups[] = { + "sdi2_ctrl", + "sdi2_data1", + "sdi2_data4", +}; + +static const char * const tp33_groups[] = { + "tp33", +}; + +static const char * const uart1_groups[] = { + "uart1_data", + "uart1_ctrl", +}; + +static const char * const uart2_groups[] = { + "uart2_data", +}; + +static const char * const uart3_groups[] = { + "uart3_data", +}; + +static const char * const usb_groups[] = { + "usb_vbus", +}; + +static const char * const usi0_groups[] = { + "usi0_cs1", + "usi0_cs2", + "usi0_cs3", + "usi0_cs4", + "usi0_cs5", + "usi0_cs6", +}; + +static const char * const usi1_groups[] = { + "usi1", +}; + +static const char * const usi2_groups[] = { + "usi2", + "usi2_cs0", + "usi2_cs1", + "usi2_cs2", +}; + +static const char * const usi3_groups[] = { + "usi3", + "usi3_cs0", +}; + +static const char * const usi4_groups[] = { + "usi4", + "usi4_cs0", + "usi4_cs1", +}; + +static const char * const usi5_groups[] = { + "usi5_a", + "usi5_cs0_a", + "usi5_cs1_a", + "usi5_cs2_a", + "usi5_b", + "usi5_cs0_b", + "usi5_cs1_b", + "usi5_cs2_b", + "usi5_cs3_b", + "usi5_cs4_b", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(ab), + SH_PFC_FUNCTION(cam), + SH_PFC_FUNCTION(cf), + SH_PFC_FUNCTION(dtv), + SH_PFC_FUNCTION(iic0), + SH_PFC_FUNCTION(iic1), + SH_PFC_FUNCTION(jtag), + SH_PFC_FUNCTION(lcd), + SH_PFC_FUNCTION(ntsc), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(sd), + SH_PFC_FUNCTION(sdi0), + SH_PFC_FUNCTION(sdi1), + SH_PFC_FUNCTION(sdi2), + SH_PFC_FUNCTION(tp33), + SH_PFC_FUNCTION(uart1), + SH_PFC_FUNCTION(uart2), + SH_PFC_FUNCTION(uart3), + SH_PFC_FUNCTION(usb), + SH_PFC_FUNCTION(usi0), + SH_PFC_FUNCTION(usi1), + SH_PFC_FUNCTION(usi2), + SH_PFC_FUNCTION(usi3), + SH_PFC_FUNCTION(usi4), + SH_PFC_FUNCTION(usi5), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1) { + 0, PORT31_FN, /* PIN: J18 */ + 0, PORT30_FN, /* PIN: H18 */ + 0, PORT29_FN, /* PIN: G18 */ + 0, PORT28_FN, /* PIN: F18 */ + 0, PORT27_FN, /* PIN: F17 */ + 0, PORT26_FN, /* PIN: F16 */ + 0, PORT25_FN, /* PIN: E20 */ + 0, PORT24_FN, /* PIN: D20 */ + FN_LCD3_1_0_PORT23, PORT23_FN, /* PIN: D19 */ + FN_LCD3_1_0_PORT22, PORT22_FN, /* PIN: C20 */ + FN_LCD3_1_0_PORT21, PORT21_FN, /* PIN: B21 */ + FN_LCD3_1_0_PORT20, PORT20_FN, /* PIN: A21 */ + FN_LCD3_PXCLKB, PORT19_FN, /* PIN: C21 */ + FN_LCD3_1_0_PORT18, PORT18_FN, /* PIN: B22 */ + 0, PORT17_FN, /* PIN: W20 */ + 0, PORT16_FN, /* PIN: W21 */ + 0, PORT15_FN, /* PIN: Y19 */ + 0, PORT14_FN, /* PIN: Y20 */ + 0, PORT13_FN, /* PIN: Y21 */ + 0, PORT12_FN, /* PIN: AA20 */ + 0, PORT11_FN, /* PIN: AA21 */ + 0, PORT10_FN, /* PIN: AA22 */ + 0, PORT9_FN, /* PIN: V15 */ + 0, PORT8_FN, /* PIN: V16 */ + 0, PORT7_FN, /* PIN: V17 */ + 0, PORT6_FN, /* PIN: V18 */ + FN_EXT_CLKI, PORT5_FN, /* PIN: U8 */ + FN_REF_CLKO, PORT4_FN, /* PIN: V8 */ + FN_ERR_RST_REQB, PORT3_FN, /* PIN: U9 */ + FN_JT_SEL, PORT2_FN, /* PIN: V9 */ + 0, PORT1_FN, /* PIN: U10 */ + 0, PORT0_FN, /* PIN: V10 */ + } + }, + { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1) { + FN_SDI1_CMD, PORT63_FN, /* PIN: AC21 */ + FN_SDI1_CKI, PORT62_FN, /* PIN: AA23 */ + FN_SDI1_CKO, PORT61_FN, /* PIN: AB22 */ + FN_SDI0_DATA7, PORT60_FN, /* PIN: Y16 */ + FN_SDI0_DATA6, PORT59_FN, /* PIN: AA16 */ + FN_SDI0_DATA5, PORT58_FN, /* PIN: Y15 */ + FN_SDI0_DATA4, PORT57_FN, /* PIN: AA15 */ + FN_SDI0_DATA3, PORT56_FN, /* PIN: Y14 */ + FN_SDI0_DATA2, PORT55_FN, /* PIN: AA14 */ + FN_SDI0_DATA1, PORT54_FN, /* PIN: Y13 */ + FN_SDI0_DATA0, PORT53_FN, /* PIN: AA13 */ + FN_SDI0_CMD, PORT52_FN, /* PIN: Y12 */ + FN_SDI0_CKI, PORT51_FN, /* PIN: AC18 */ + FN_SDI0_CKO, PORT50_FN, /* PIN: AB18 */ + 0, PORT49_FN, /* PIN: AB16 */ + FN_SD_CKI, PORT48_FN, /* PIN: AC19 */ + FN_IIC_1_0_PORT47, PORT47_FN, /* PIN: Y8 */ + FN_IIC_1_0_PORT46, PORT46_FN, /* PIN: Y9 */ + FN_IIC0_SDA, PORT45_FN, /* PIN: AA8 */ + FN_IIC0_SCL, PORT44_FN, /* PIN: AA9 */ + FN_LCD3_11_10_PORT43, PORT43_FN, /* PIN: A15 */ + FN_LCD3_11_10_PORT42, PORT42_FN, /* PIN: A16 */ + FN_LCD3_11_10_PORT41, PORT41_FN, /* PIN: A17 */ + FN_LCD3_11_10_PORT40, PORT40_FN, /* PIN: A18 */ + FN_LCD3_9_8_PORT39, PORT39_FN, /* PIN: D18 */ + FN_LCD3_9_8_PORT38, PORT38_FN, /* PIN: C18 */ + FN_LCD3_R5, PORT37_FN, /* PIN: B18 */ + FN_LCD3_R4, PORT36_FN, /* PIN: C19 */ + FN_LCD3_R3, PORT35_FN, /* PIN: B19 */ + FN_LCD3_R2, PORT34_FN, /* PIN: A19 */ + FN_LCD3_R1, PORT33_FN, /* PIN: B20 */ + FN_LCD3_R0, PORT32_FN, /* PIN: A20 */ + } + }, + { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1) { + FN_AB_1_0_PORT95, PORT95_FN, /* PIN: L21 */ + FN_AB_1_0_PORT94, PORT94_FN, /* PIN: K21 */ + FN_AB_1_0_PORT93, PORT93_FN, /* PIN: J21 */ + FN_AB_7_6_PORT92, PORT92_FN, /* PIN: J22 */ + FN_AB_7_6_PORT91, PORT91_FN, /* PIN: H21 */ + FN_AB_5_4_PORT90, PORT90_FN, /* PIN: H22 */ + FN_AB_5_4_PORT89, PORT89_FN, /* PIN: H23 */ + FN_AB_3_2_PORT88, PORT88_FN, /* PIN: G21 */ + FN_AB_3_2_PORT87, PORT87_FN, /* PIN: G22 */ + FN_AB_3_2_PORT86, PORT86_FN, /* PIN: G23 */ + FN_AB_3_2_PORT85, PORT85_FN, /* PIN: F21 */ + FN_AB_1_0_PORT84, PORT84_FN, /* PIN: F22 */ + FN_AB_1_0_PORT83, PORT83_FN, /* PIN: F23 */ + FN_AB_1_0_PORT82, PORT82_FN, /* PIN: E22 */ + FN_AB_1_0_PORT81, PORT81_FN, /* PIN: E23 */ + FN_AB_1_0_PORT80, PORT80_FN, /* PIN: D22 */ + FN_AB_1_0_PORT79, PORT79_FN, /* PIN: D23 */ + FN_AB_1_0_PORT78, PORT78_FN, /* PIN: C22 */ + FN_AB_1_0_PORT77, PORT77_FN, /* PIN: C23 */ + FN_AB_1_0_PORT76, PORT76_FN, /* PIN: K20 */ + FN_AB_1_0_PORT75, PORT75_FN, /* PIN: L20 */ + FN_AB_1_0_PORT74, PORT74_FN, /* PIN: H20 */ + FN_AB_1_0_PORT73, PORT73_FN, /* PIN: J20 */ + FN_AB_1_0_PORT72, PORT72_FN, /* PIN: G20 */ + FN_AB_1_0_PORT71, PORT71_FN, /* PIN: F20 */ + FN_AB_CSB1, PORT70_FN, /* PIN: E21 */ + FN_AB_CSB0, PORT69_FN, /* PIN: D21 */ + FN_AB_CLK, PORT68_FN, /* PIN: J23 */ + FN_SDI1_DATA3, PORT67_FN, /* PIN: AA19 */ + FN_SDI1_DATA2, PORT66_FN, /* PIN: AB19 */ + FN_SDI1_DATA1, PORT65_FN, /* PIN: AB20 */ + FN_SDI1_DATA0, PORT64_FN, /* PIN: AB21 */ + } + }, + { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1) { + FN_NTSC_DATA4, PORT127_FN, /* PIN: T20 */ + FN_NTSC_DATA3, PORT126_FN, /* PIN: R18 */ + FN_NTSC_DATA2, PORT125_FN, /* PIN: R20 */ + FN_NTSC_DATA1, PORT124_FN, /* PIN: P18 */ + FN_NTSC_DATA0, PORT123_FN, /* PIN: P20 */ + FN_NTSC_CLK, PORT122_FN, /* PIN: V20 */ + FN_USI_9_8_PORT121, PORT121_FN, /* PIN: Y5 */ + FN_USI_9_8_PORT120, PORT120_FN, /* PIN: AA4 */ + FN_USI_7_6_PORT119, PORT119_FN, /* PIN: AB3 */ + FN_USI_5_4_PORT118, PORT118_FN, /* PIN: AB4 */ + FN_USI_5_4_PORT117, PORT117_FN, /* PIN: AC3 */ + FN_USI_5_4_PORT116, PORT116_FN, /* PIN: AC4 */ + FN_USI_5_4_PORT115, PORT115_FN, /* PIN: AC5 */ + FN_USI_3_2_PORT114, PORT114_FN, /* PIN: Y6 */ + FN_USI_3_2_PORT113, PORT113_FN, /* PIN: AA7 */ + FN_USI_1_0_PORT112, PORT112_FN, /* PIN: Y7 */ + FN_USI_1_0_PORT111, PORT111_FN, /* PIN: AA5 */ + FN_USI_1_0_PORT110, PORT110_FN, /* PIN: AA6 */ + FN_USI_1_0_PORT109, PORT109_FN, /* PIN: AB5 */ + FN_USI1_DO, PORT108_FN, /* PIN: D10 */ + FN_USI1_DI, PORT107_FN, /* PIN: C10 */ + FN_USI0_CS2, PORT106_FN, /* PIN: B9 */ + FN_USI0_CS1, PORT105_FN, /* PIN: B8 */ + FN_AB_13_12_PORT104, PORT104_FN, /* PIN: M17 */ + FN_AB_13_12_PORT103, PORT103_FN, /* PIN: L17 */ + FN_AB_11_10_PORT102, PORT102_FN, /* PIN: N18 */ + FN_AB_11_10_PORT101, PORT101_FN, /* PIN: M18 */ + FN_AB_11_10_PORT100, PORT100_FN, /* PIN: L18 */ + FN_AB_9_8_PORT99, PORT99_FN, /* PIN: N20 */ + FN_AB_9_8_PORT98, PORT98_FN, /* PIN: M20 */ + FN_AB_9_8_PORT97, PORT97_FN, /* PIN: N21 */ + FN_AB_A20, PORT96_FN, /* PIN: M21 */ + } + }, + { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1) { + 0, 0, + FN_UART_1_0_PORT158, PORT158_FN, /* PIN: AB10 */ + FN_UART_1_0_PORT157, PORT157_FN, /* PIN: AA10 */ + FN_UART1_TX, PORT156_FN, /* PIN: Y10 */ + FN_UART1_RX, PORT155_FN, /* PIN: Y11 */ + FN_LOWPWR, PORT154_FN, /* PIN: A12 */ + FN_USB_VBUS, PORT153_FN, /* PIN: AA12 */ + FN_JT_TDOEN, PORT152_FN, /* PIN: F13 */ + FN_JT_TDO, PORT151_FN, /* PIN: D13 */ + FN_HSI_1_0_PORT150, PORT150_FN, /* PIN: M22 */ + FN_HSI_1_0_PORT149, PORT149_FN, /* PIN: M23 */ + FN_HSI_1_0_PORT148, PORT148_FN, /* PIN: N23 */ + FN_HSI_1_0_PORT147, PORT147_FN, /* PIN: N22 */ + FN_HSI_1_0_PORT146, PORT146_FN, /* PIN: L22 */ + FN_HSI_1_0_PORT145, PORT145_FN, /* PIN: L23 */ + FN_HSI_1_0_PORT144, PORT144_FN, /* PIN: K23 */ + FN_HSI_1_0_PORT143, PORT143_FN, /* PIN: K22 */ + FN_CAM_YUV7, PORT142_FN, /* PIN: V23 */ + FN_CAM_YUV6, PORT141_FN, /* PIN: V22 */ + FN_CAM_YUV5, PORT140_FN, /* PIN: U23 */ + FN_CAM_YUV4, PORT139_FN, /* PIN: U22 */ + FN_CAM_YUV3, PORT138_FN, /* PIN: U21 */ + FN_CAM_YUV2, PORT137_FN, /* PIN: T23 */ + FN_CAM_YUV1, PORT136_FN, /* PIN: T22 */ + FN_CAM_YUV0, PORT135_FN, /* PIN: T21 */ + FN_CAM_HS, PORT134_FN, /* PIN: V21 */ + FN_CAM_VS, PORT133_FN, /* PIN: W22 */ + FN_CAM_CLKI, PORT132_FN, /* PIN: Y23 */ + FN_CAM_CLKO, PORT131_FN, /* PIN: W23 */ + FN_NTSC_DATA7, PORT130_FN, /* PIN: U18 */ + FN_NTSC_DATA6, PORT129_FN, /* PIN: U20 */ + FN_NTSC_DATA5, PORT128_FN, /* PIN: T18 */ + } + }, + { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 2, 2, 2, 2, 2, 2) { + /* 31 - 12 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* 11 - 10 */ + FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01, + FN_SEL_LCD3_11_10_10, 0, + /* 9 - 8 */ + FN_SEL_LCD3_9_8_00, 0, FN_SEL_LCD3_9_8_10, 0, + /* 7 - 2 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* 1 - 0 */ + FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) { + /* 31 - 2 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* 1 - 0 */ + FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) { + /* 31 - 2 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* 1 - 0 */ + FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 2, 2, 2, 2, 2, 2, 2, 2) { + /* 31 - 14 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + /* 13 - 12 */ + FN_SEL_AB_13_12_00, 0, FN_SEL_AB_13_12_10, 0, + /* 11 - 10 */ + FN_SEL_AB_11_10_00, 0, FN_SEL_AB_11_10_10, 0, + /* 9 - 8 */ + FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10, 0, + /* 7 - 6 */ + FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01, FN_SEL_AB_7_6_10, 0, + /* 5 - 4 */ + FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01, + FN_SEL_AB_5_4_10, FN_SEL_AB_5_4_11, + /* 3 - 2 */ + FN_SEL_AB_3_2_00, FN_SEL_AB_3_2_01, + FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11, + /* 1 - 0 */ + FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0, + } + }, + { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2) { + /* 31 - 10 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* 9 - 8 */ + FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01, 0, 0, + /* 7 - 6 */ + FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01, 0, 0, + /* 5 - 4 */ + FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01, 0, 0, + /* 3 - 2 */ + FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0, + /* 1 - 0 */ + FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) { + /* 31 - 2 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* 1 - 0 */ + FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0, + } + }, + { }, +}; + +const struct sh_pfc_soc_info emev2_pinmux_info = { + .name = "emev2_pfc", + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 9a179c94b4dc..80c1843bb6ad 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -2241,6 +2241,13 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; /* - MMCIF0 ----------------------------------------------------------------- */ static const unsigned int mmc0_data1_pins[] = { /* D[0] */ @@ -3873,6 +3880,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(mlb_3pin), SH_PFC_PIN_GROUP(mmc0_data1), SH_PFC_PIN_GROUP(mmc0_data4), SH_PFC_PIN_GROUP(mmc0_data8), @@ -4198,6 +4206,10 @@ static const char * const intc_groups[] = { "intc_irq3", }; +static const char * const mlb_groups[] = { + "mlb_3pin", +}; + static const char * const mmc0_groups[] = { "mmc0_data1", "mmc0_data4", @@ -4511,6 +4523,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(iic2), SH_PFC_FUNCTION(iic3), SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mlb), SH_PFC_FUNCTION(mmc0), SH_PFC_FUNCTION(mmc1), SH_PFC_FUNCTION(msiof0), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index c6e5deba238e..fdd2c8729791 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -378,7 +378,7 @@ enum { /* IPSR16 */ FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C, FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C, - FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C, + FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C, FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, @@ -764,7 +764,7 @@ enum { GLO_SDATA_C_MARK, VI1_DATA6_C_MARK, HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK, GLO_SS_C_MARK, VI1_DATA7_C_MARK, - HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK, + HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK, HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK, HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK, PINMUX_MARK_END, @@ -1664,7 +1664,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0), PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), - PINMUX_IPSR_DATA(IP16_7_6, MLB_CK), + PINMUX_IPSR_DATA(IP16_7_6, MLB_CLK), PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2), PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N), @@ -2391,6 +2391,13 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; /* - MMCIF ------------------------------------------------------------------ */ static const unsigned int mmc_data1_pins[] = { /* D[0] */ @@ -4267,6 +4274,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(mlb_3pin), SH_PFC_PIN_GROUP(mmc_data1), SH_PFC_PIN_GROUP(mmc_data4), SH_PFC_PIN_GROUP(mmc_data8), @@ -4648,6 +4656,10 @@ static const char * const intc_groups[] = { "intc_irq3", }; +static const char * const mlb_groups[] = { + "mlb_3pin", +}; + static const char * const mmc_groups[] = { "mmc_data1", "mmc_data4", @@ -4972,6 +4984,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c7), SH_PFC_FUNCTION(i2c8), SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mlb), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), @@ -5974,7 +5987,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP16_9_8 [2] */ FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, /* IP16_7_6 [2] */ - FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C, + FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C, /* IP16_5_3 [3] */ FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c deleted file mode 100644 index 8211f66a2f68..000000000000 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ /dev/null @@ -1,2645 +0,0 @@ -/* - * sh7372 processor support - PFC hardware block - * - * Copyright (C) 2010 Kuninori Morimoto <morimoto.kuninori@renesas.com> - * - * Based on - * sh7367 processor support - PFC hardware block - * Copyright (C) 2010 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include <linux/io.h> -#include <linux/kernel.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/sh_intc.h> - -#include "core.h" -#include "sh_pfc.h" - -#define CPU_ALL_PORT(fn, pfx, sfx) \ - PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \ - PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \ - PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \ - PORT_10(140, fn, pfx##14, sfx), PORT_10(150, fn, pfx##15, sfx), \ - PORT_10(160, fn, pfx##16, sfx), PORT_10(170, fn, pfx##17, sfx), \ - PORT_10(180, fn, pfx##18, sfx), PORT_1(190, fn, pfx##190, sfx) - -#define IRQC_PIN_MUX(irq, pin) \ -static const unsigned int intc_irq##irq##_pins[] = { \ - pin, \ -}; \ -static const unsigned int intc_irq##irq##_mux[] = { \ - IRQ##irq##_MARK, \ -} - -#define IRQC_PINS_MUX(irq, pin0, pin1) \ -static const unsigned int intc_irq##irq##_0_pins[] = { \ - pin0, \ -}; \ -static const unsigned int intc_irq##irq##_0_mux[] = { \ - IRQ##irq##_##pin0##_MARK, \ -}; \ -static const unsigned int intc_irq##irq##_1_pins[] = { \ - pin1, \ -}; \ -static const unsigned int intc_irq##irq##_1_mux[] = { \ - IRQ##irq##_##pin1##_MARK, \ -} - -enum { - PINMUX_RESERVED = 0, - - /* PORT0_DATA -> PORT190_DATA */ - PINMUX_DATA_BEGIN, - PORT_ALL(DATA), - PINMUX_DATA_END, - - /* PORT0_IN -> PORT190_IN */ - PINMUX_INPUT_BEGIN, - PORT_ALL(IN), - PINMUX_INPUT_END, - - /* PORT0_OUT -> PORT190_OUT */ - PINMUX_OUTPUT_BEGIN, - PORT_ALL(OUT), - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT190_FN_IN */ - PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT190_FN_OUT */ - PORT_ALL(FN0), /* PORT0_FN0 -> PORT190_FN0 */ - PORT_ALL(FN1), /* PORT0_FN1 -> PORT190_FN1 */ - PORT_ALL(FN2), /* PORT0_FN2 -> PORT190_FN2 */ - PORT_ALL(FN3), /* PORT0_FN3 -> PORT190_FN3 */ - PORT_ALL(FN4), /* PORT0_FN4 -> PORT190_FN4 */ - PORT_ALL(FN5), /* PORT0_FN5 -> PORT190_FN5 */ - PORT_ALL(FN6), /* PORT0_FN6 -> PORT190_FN6 */ - PORT_ALL(FN7), /* PORT0_FN7 -> PORT190_FN7 */ - - MSEL1CR_31_0, MSEL1CR_31_1, - MSEL1CR_30_0, MSEL1CR_30_1, - MSEL1CR_29_0, MSEL1CR_29_1, - MSEL1CR_28_0, MSEL1CR_28_1, - MSEL1CR_27_0, MSEL1CR_27_1, - MSEL1CR_26_0, MSEL1CR_26_1, - MSEL1CR_16_0, MSEL1CR_16_1, - MSEL1CR_15_0, MSEL1CR_15_1, - MSEL1CR_14_0, MSEL1CR_14_1, - MSEL1CR_13_0, MSEL1CR_13_1, - MSEL1CR_12_0, MSEL1CR_12_1, - MSEL1CR_9_0, MSEL1CR_9_1, - MSEL1CR_8_0, MSEL1CR_8_1, - MSEL1CR_7_0, MSEL1CR_7_1, - MSEL1CR_6_0, MSEL1CR_6_1, - MSEL1CR_4_0, MSEL1CR_4_1, - MSEL1CR_3_0, MSEL1CR_3_1, - MSEL1CR_2_0, MSEL1CR_2_1, - MSEL1CR_0_0, MSEL1CR_0_1, - - MSEL3CR_27_0, MSEL3CR_27_1, - MSEL3CR_26_0, MSEL3CR_26_1, - MSEL3CR_21_0, MSEL3CR_21_1, - MSEL3CR_20_0, MSEL3CR_20_1, - MSEL3CR_15_0, MSEL3CR_15_1, - MSEL3CR_9_0, MSEL3CR_9_1, - MSEL3CR_6_0, MSEL3CR_6_1, - - MSEL4CR_19_0, MSEL4CR_19_1, - MSEL4CR_18_0, MSEL4CR_18_1, - MSEL4CR_17_0, MSEL4CR_17_1, - MSEL4CR_16_0, MSEL4CR_16_1, - MSEL4CR_15_0, MSEL4CR_15_1, - MSEL4CR_14_0, MSEL4CR_14_1, - MSEL4CR_10_0, MSEL4CR_10_1, - MSEL4CR_6_0, MSEL4CR_6_1, - MSEL4CR_4_0, MSEL4CR_4_1, - MSEL4CR_1_0, MSEL4CR_1_1, - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - - /* IRQ */ - IRQ0_6_MARK, IRQ0_162_MARK, IRQ1_MARK, IRQ2_4_MARK, - IRQ2_5_MARK, IRQ3_8_MARK, IRQ3_16_MARK, IRQ4_17_MARK, - IRQ4_163_MARK, IRQ5_MARK, IRQ6_39_MARK, IRQ6_164_MARK, - IRQ7_40_MARK, IRQ7_167_MARK, IRQ8_41_MARK, IRQ8_168_MARK, - IRQ9_42_MARK, IRQ9_169_MARK, IRQ10_MARK, IRQ11_MARK, - IRQ12_80_MARK, IRQ12_137_MARK, IRQ13_81_MARK, IRQ13_145_MARK, - IRQ14_82_MARK, IRQ14_146_MARK, IRQ15_83_MARK, IRQ15_147_MARK, - IRQ16_84_MARK, IRQ16_170_MARK, IRQ17_MARK, IRQ18_MARK, - IRQ19_MARK, IRQ20_MARK, IRQ21_MARK, IRQ22_MARK, - IRQ23_MARK, IRQ24_MARK, IRQ25_MARK, IRQ26_121_MARK, - IRQ26_172_MARK, IRQ27_122_MARK, IRQ27_180_MARK, IRQ28_123_MARK, - IRQ28_181_MARK, IRQ29_129_MARK, IRQ29_182_MARK, IRQ30_130_MARK, - IRQ30_183_MARK, IRQ31_138_MARK, IRQ31_184_MARK, - - /* MSIOF0 */ - MSIOF0_TSYNC_MARK, MSIOF0_TSCK_MARK, MSIOF0_RXD_MARK, - MSIOF0_RSCK_MARK, MSIOF0_RSYNC_MARK, MSIOF0_MCK0_MARK, - MSIOF0_MCK1_MARK, MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, - MSIOF0_TXD_MARK, - - /* MSIOF1 */ - MSIOF1_TSCK_39_MARK, MSIOF1_TSYNC_40_MARK, - MSIOF1_TSCK_88_MARK, MSIOF1_TSYNC_89_MARK, - MSIOF1_TXD_41_MARK, MSIOF1_RXD_42_MARK, - MSIOF1_TXD_90_MARK, MSIOF1_RXD_91_MARK, - MSIOF1_SS1_43_MARK, MSIOF1_SS2_44_MARK, - MSIOF1_SS1_92_MARK, MSIOF1_SS2_93_MARK, - MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK, - MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK, - - /* MSIOF2 */ - MSIOF2_RSCK_MARK, MSIOF2_RSYNC_MARK, MSIOF2_MCK0_MARK, - MSIOF2_MCK1_MARK, MSIOF2_SS1_MARK, MSIOF2_SS2_MARK, - MSIOF2_TSYNC_MARK, MSIOF2_TSCK_MARK, MSIOF2_RXD_MARK, - MSIOF2_TXD_MARK, - - /* BBIF1 */ - BBIF1_RXD_MARK, BBIF1_TSYNC_MARK, BBIF1_TSCK_MARK, - BBIF1_TXD_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK, - BBIF1_FLOW_MARK, BB_RX_FLOW_N_MARK, - - /* BBIF2 */ - BBIF2_TSCK1_MARK, BBIF2_TSYNC1_MARK, - BBIF2_TXD1_MARK, BBIF2_RXD_MARK, - - /* FSI */ - FSIACK_MARK, FSIBCK_MARK, FSIAILR_MARK, FSIAIBT_MARK, - FSIAISLD_MARK, FSIAOMC_MARK, FSIAOLR_MARK, FSIAOBT_MARK, - FSIAOSLD_MARK, FSIASPDIF_11_MARK, FSIASPDIF_15_MARK, - - /* FMSI */ - FMSOCK_MARK, FMSOOLR_MARK, FMSIOLR_MARK, FMSOOBT_MARK, - FMSIOBT_MARK, FMSOSLD_MARK, FMSOILR_MARK, FMSIILR_MARK, - FMSOIBT_MARK, FMSIIBT_MARK, FMSISLD_MARK, FMSICK_MARK, - - /* SCIFA0 */ - SCIFA0_TXD_MARK, SCIFA0_RXD_MARK, SCIFA0_SCK_MARK, - SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, - - /* SCIFA1 */ - SCIFA1_TXD_MARK, SCIFA1_RXD_MARK, SCIFA1_SCK_MARK, - SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, - - /* SCIFA2 */ - SCIFA2_CTS1_MARK, SCIFA2_RTS1_MARK, SCIFA2_TXD1_MARK, - SCIFA2_RXD1_MARK, SCIFA2_SCK1_MARK, - - /* SCIFA3 */ - SCIFA3_CTS_43_MARK, SCIFA3_CTS_140_MARK, SCIFA3_RTS_44_MARK, - SCIFA3_RTS_141_MARK, SCIFA3_SCK_MARK, SCIFA3_TXD_MARK, - SCIFA3_RXD_MARK, - - /* SCIFA4 */ - SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, - - /* SCIFA5 */ - SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, - - /* SCIFB */ - SCIFB_SCK_MARK, SCIFB_RTS_MARK, SCIFB_CTS_MARK, - SCIFB_TXD_MARK, SCIFB_RXD_MARK, - - /* CEU */ - VIO_HD_MARK, VIO_CKO1_MARK, VIO_CKO2_MARK, VIO_VD_MARK, - VIO_CLK_MARK, VIO_FIELD_MARK, VIO_CKO_MARK, - VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK, - VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK, - VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK, - VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK, - - /* USB0 */ - IDIN_0_MARK, EXTLP_0_MARK, OVCN2_0_MARK, PWEN_0_MARK, - OVCN_0_MARK, VBUS0_0_MARK, - - /* USB1 */ - IDIN_1_18_MARK, IDIN_1_113_MARK, - PWEN_1_115_MARK, PWEN_1_138_MARK, - OVCN_1_114_MARK, OVCN_1_162_MARK, - EXTLP_1_MARK, OVCN2_1_MARK, - VBUS0_1_MARK, - - /* GPIO */ - GPI0_MARK, GPI1_MARK, GPO0_MARK, GPO1_MARK, - - /* BSC */ - BS_MARK, WE1_MARK, - CKO_MARK, WAIT_MARK, RDWR_MARK, - - A0_MARK, A1_MARK, A2_MARK, A3_MARK, - A6_MARK, A7_MARK, A8_MARK, A9_MARK, - A10_MARK, A11_MARK, A12_MARK, A13_MARK, - A14_MARK, A15_MARK, A16_MARK, A17_MARK, - A18_MARK, A19_MARK, A20_MARK, A21_MARK, - A22_MARK, A23_MARK, A24_MARK, A25_MARK, - A26_MARK, - - CS0_MARK, CS2_MARK, CS4_MARK, - CS5A_MARK, CS5B_MARK, CS6A_MARK, - - /* BSC/FLCTL */ - RD_FSC_MARK, WE0_FWE_MARK, A4_FOE_MARK, A5_FCDE_MARK, - D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, - D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, - D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, - D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, - - /* MMCIF(1) */ - MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, - MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, - MMCCMD0_MARK, MMCCLK0_MARK, - - /* MMCIF(2) */ - MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, - MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, - MMCCLK1_MARK, MMCCMD1_MARK, - - /* SPU2 */ - VINT_I_MARK, - - /* FLCTL */ - FCE1_MARK, FCE0_MARK, FRB_MARK, - - /* HSI */ - GP_RX_FLAG_MARK, GP_RX_DATA_MARK, GP_TX_READY_MARK, - GP_RX_WAKE_MARK, MP_TX_FLAG_MARK, MP_TX_DATA_MARK, - MP_RX_READY_MARK, MP_TX_WAKE_MARK, - - /* MFI */ - MFIv6_MARK, - MFIv4_MARK, - - MEMC_CS0_MARK, MEMC_BUSCLK_MEMC_A0_MARK, - MEMC_CS1_MEMC_A1_MARK, MEMC_ADV_MEMC_DREQ0_MARK, - MEMC_WAIT_MEMC_DREQ1_MARK, MEMC_NOE_MARK, - MEMC_NWE_MARK, MEMC_INT_MARK, - - MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, - MEMC_AD3_MARK, MEMC_AD4_MARK, MEMC_AD5_MARK, - MEMC_AD6_MARK, MEMC_AD7_MARK, MEMC_AD8_MARK, - MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK, - MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, - MEMC_AD15_MARK, - - /* SIM */ - SIM_RST_MARK, SIM_CLK_MARK, SIM_D_MARK, - - /* TPU */ - TPU0TO0_MARK, TPU0TO1_MARK, - TPU0TO2_93_MARK, TPU0TO2_99_MARK, - TPU0TO3_MARK, - - /* I2C2 */ - I2C_SCL2_MARK, I2C_SDA2_MARK, - - /* I2C3(1) */ - I2C_SCL3_MARK, I2C_SDA3_MARK, - - /* I2C3(2) */ - I2C_SCL3S_MARK, I2C_SDA3S_MARK, - - /* I2C4(2) */ - I2C_SCL4_MARK, I2C_SDA4_MARK, - - /* I2C4(2) */ - I2C_SCL4S_MARK, I2C_SDA4S_MARK, - - /* KEYSC */ - KEYOUT0_MARK, KEYIN0_121_MARK, KEYIN0_136_MARK, - KEYOUT1_MARK, KEYIN1_122_MARK, KEYIN1_135_MARK, - KEYOUT2_MARK, KEYIN2_123_MARK, KEYIN2_134_MARK, - KEYOUT3_MARK, KEYIN3_124_MARK, KEYIN3_133_MARK, - KEYOUT4_MARK, KEYIN4_MARK, - KEYOUT5_MARK, KEYIN5_MARK, - KEYOUT6_MARK, KEYIN6_MARK, - KEYOUT7_MARK, KEYIN7_MARK, - - /* LCDC */ - LCDC0_SELECT_MARK, - LCDC1_SELECT_MARK, - LCDHSYN_MARK, LCDCS_MARK, LCDVSYN_MARK, LCDDCK_MARK, - LCDWR_MARK, LCDRD_MARK, LCDDISP_MARK, LCDRS_MARK, - LCDLCLK_MARK, LCDDON_MARK, - - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, - LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, - LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK, - LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK, - - /* IRDA */ - IRDA_OUT_MARK, IRDA_IN_MARK, IRDA_FIRSEL_MARK, - IROUT_139_MARK, IROUT_140_MARK, - - /* TSIF1 */ - TS0_1SELECT_MARK, - TS0_2SELECT_MARK, - TS1_1SELECT_MARK, - TS1_2SELECT_MARK, - - TS_SPSYNC1_MARK, TS_SDAT1_MARK, - TS_SDEN1_MARK, TS_SCK1_MARK, - - /* TSIF2 */ - TS_SPSYNC2_MARK, TS_SDAT2_MARK, - TS_SDEN2_MARK, TS_SCK2_MARK, - - /* HDMI */ - HDMI_HPD_MARK, HDMI_CEC_MARK, - - /* SDHI0 */ - SDHICLK0_MARK, SDHICD0_MARK, - SDHICMD0_MARK, SDHIWP0_MARK, - SDHID0_0_MARK, SDHID0_1_MARK, - SDHID0_2_MARK, SDHID0_3_MARK, - - /* SDHI1 */ - SDHICLK1_MARK, SDHICMD1_MARK, SDHID1_0_MARK, - SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, - - /* SDHI2 */ - SDHICLK2_MARK, SDHICMD2_MARK, SDHID2_0_MARK, - SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, - - /* SDENC */ - SDENC_CPG_MARK, - SDENC_DV_CLKI_MARK, - - PINMUX_MARK_END, -}; - -static const u16 pinmux_data[] = { - PINMUX_DATA_ALL(), - - /* IRQ */ - PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0), - PINMUX_DATA(IRQ0_162_MARK, PORT162_FN0, MSEL1CR_0_1), - PINMUX_DATA(IRQ1_MARK, PORT12_FN0), - PINMUX_DATA(IRQ2_4_MARK, PORT4_FN0, MSEL1CR_2_0), - PINMUX_DATA(IRQ2_5_MARK, PORT5_FN0, MSEL1CR_2_1), - PINMUX_DATA(IRQ3_8_MARK, PORT8_FN0, MSEL1CR_3_0), - PINMUX_DATA(IRQ3_16_MARK, PORT16_FN0, MSEL1CR_3_1), - PINMUX_DATA(IRQ4_17_MARK, PORT17_FN0, MSEL1CR_4_0), - PINMUX_DATA(IRQ4_163_MARK, PORT163_FN0, MSEL1CR_4_1), - PINMUX_DATA(IRQ5_MARK, PORT18_FN0), - PINMUX_DATA(IRQ6_39_MARK, PORT39_FN0, MSEL1CR_6_0), - PINMUX_DATA(IRQ6_164_MARK, PORT164_FN0, MSEL1CR_6_1), - PINMUX_DATA(IRQ7_40_MARK, PORT40_FN0, MSEL1CR_7_1), - PINMUX_DATA(IRQ7_167_MARK, PORT167_FN0, MSEL1CR_7_0), - PINMUX_DATA(IRQ8_41_MARK, PORT41_FN0, MSEL1CR_8_1), - PINMUX_DATA(IRQ8_168_MARK, PORT168_FN0, MSEL1CR_8_0), - PINMUX_DATA(IRQ9_42_MARK, PORT42_FN0, MSEL1CR_9_0), - PINMUX_DATA(IRQ9_169_MARK, PORT169_FN0, MSEL1CR_9_1), - PINMUX_DATA(IRQ10_MARK, PORT65_FN0, MSEL1CR_9_1), - PINMUX_DATA(IRQ11_MARK, PORT67_FN0), - PINMUX_DATA(IRQ12_80_MARK, PORT80_FN0, MSEL1CR_12_0), - PINMUX_DATA(IRQ12_137_MARK, PORT137_FN0, MSEL1CR_12_1), - PINMUX_DATA(IRQ13_81_MARK, PORT81_FN0, MSEL1CR_13_0), - PINMUX_DATA(IRQ13_145_MARK, PORT145_FN0, MSEL1CR_13_1), - PINMUX_DATA(IRQ14_82_MARK, PORT82_FN0, MSEL1CR_14_0), - PINMUX_DATA(IRQ14_146_MARK, PORT146_FN0, MSEL1CR_14_1), - PINMUX_DATA(IRQ15_83_MARK, PORT83_FN0, MSEL1CR_15_0), - PINMUX_DATA(IRQ15_147_MARK, PORT147_FN0, MSEL1CR_15_1), - PINMUX_DATA(IRQ16_84_MARK, PORT84_FN0, MSEL1CR_16_0), - PINMUX_DATA(IRQ16_170_MARK, PORT170_FN0, MSEL1CR_16_1), - PINMUX_DATA(IRQ17_MARK, PORT85_FN0), - PINMUX_DATA(IRQ18_MARK, PORT86_FN0), - PINMUX_DATA(IRQ19_MARK, PORT87_FN0), - PINMUX_DATA(IRQ20_MARK, PORT92_FN0), - PINMUX_DATA(IRQ21_MARK, PORT93_FN0), - PINMUX_DATA(IRQ22_MARK, PORT94_FN0), - PINMUX_DATA(IRQ23_MARK, PORT95_FN0), - PINMUX_DATA(IRQ24_MARK, PORT112_FN0), - PINMUX_DATA(IRQ25_MARK, PORT119_FN0), - PINMUX_DATA(IRQ26_121_MARK, PORT121_FN0, MSEL1CR_26_1), - PINMUX_DATA(IRQ26_172_MARK, PORT172_FN0, MSEL1CR_26_0), - PINMUX_DATA(IRQ27_122_MARK, PORT122_FN0, MSEL1CR_27_1), - PINMUX_DATA(IRQ27_180_MARK, PORT180_FN0, MSEL1CR_27_0), - PINMUX_DATA(IRQ28_123_MARK, PORT123_FN0, MSEL1CR_28_1), - PINMUX_DATA(IRQ28_181_MARK, PORT181_FN0, MSEL1CR_28_0), - PINMUX_DATA(IRQ29_129_MARK, PORT129_FN0, MSEL1CR_29_1), - PINMUX_DATA(IRQ29_182_MARK, PORT182_FN0, MSEL1CR_29_0), - PINMUX_DATA(IRQ30_130_MARK, PORT130_FN0, MSEL1CR_30_1), - PINMUX_DATA(IRQ30_183_MARK, PORT183_FN0, MSEL1CR_30_0), - PINMUX_DATA(IRQ31_138_MARK, PORT138_FN0, MSEL1CR_31_1), - PINMUX_DATA(IRQ31_184_MARK, PORT184_FN0, MSEL1CR_31_0), - - /* Function 1 */ - PINMUX_DATA(BBIF2_TSCK1_MARK, PORT0_FN1), - PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT1_FN1), - PINMUX_DATA(BBIF2_TXD1_MARK, PORT2_FN1), - PINMUX_DATA(BBIF2_RXD_MARK, PORT3_FN1), - PINMUX_DATA(FSIACK_MARK, PORT4_FN1), - PINMUX_DATA(FSIAILR_MARK, PORT5_FN1), - PINMUX_DATA(FSIAIBT_MARK, PORT6_FN1), - PINMUX_DATA(FSIAISLD_MARK, PORT7_FN1), - PINMUX_DATA(FSIAOMC_MARK, PORT8_FN1), - PINMUX_DATA(FSIAOLR_MARK, PORT9_FN1), - PINMUX_DATA(FSIAOBT_MARK, PORT10_FN1), - PINMUX_DATA(FSIAOSLD_MARK, PORT11_FN1), - PINMUX_DATA(FMSOCK_MARK, PORT12_FN1), - PINMUX_DATA(FMSOOLR_MARK, PORT13_FN1), - PINMUX_DATA(FMSOOBT_MARK, PORT14_FN1), - PINMUX_DATA(FMSOSLD_MARK, PORT15_FN1), - PINMUX_DATA(FMSOILR_MARK, PORT16_FN1), - PINMUX_DATA(FMSOIBT_MARK, PORT17_FN1), - PINMUX_DATA(FMSISLD_MARK, PORT18_FN1), - PINMUX_DATA(A0_MARK, PORT19_FN1), - PINMUX_DATA(A1_MARK, PORT20_FN1), - PINMUX_DATA(A2_MARK, PORT21_FN1), - PINMUX_DATA(A3_MARK, PORT22_FN1), - PINMUX_DATA(A4_FOE_MARK, PORT23_FN1), - PINMUX_DATA(A5_FCDE_MARK, PORT24_FN1), - PINMUX_DATA(A6_MARK, PORT25_FN1), - PINMUX_DATA(A7_MARK, PORT26_FN1), - PINMUX_DATA(A8_MARK, PORT27_FN1), - PINMUX_DATA(A9_MARK, PORT28_FN1), - PINMUX_DATA(A10_MARK, PORT29_FN1), - PINMUX_DATA(A11_MARK, PORT30_FN1), - PINMUX_DATA(A12_MARK, PORT31_FN1), - PINMUX_DATA(A13_MARK, PORT32_FN1), - PINMUX_DATA(A14_MARK, PORT33_FN1), - PINMUX_DATA(A15_MARK, PORT34_FN1), - PINMUX_DATA(A16_MARK, PORT35_FN1), - PINMUX_DATA(A17_MARK, PORT36_FN1), - PINMUX_DATA(A18_MARK, PORT37_FN1), - PINMUX_DATA(A19_MARK, PORT38_FN1), - PINMUX_DATA(A20_MARK, PORT39_FN1), - PINMUX_DATA(A21_MARK, PORT40_FN1), - PINMUX_DATA(A22_MARK, PORT41_FN1), - PINMUX_DATA(A23_MARK, PORT42_FN1), - PINMUX_DATA(A24_MARK, PORT43_FN1), - PINMUX_DATA(A25_MARK, PORT44_FN1), - PINMUX_DATA(A26_MARK, PORT45_FN1), - PINMUX_DATA(D0_NAF0_MARK, PORT46_FN1), - PINMUX_DATA(D1_NAF1_MARK, PORT47_FN1), - PINMUX_DATA(D2_NAF2_MARK, PORT48_FN1), - PINMUX_DATA(D3_NAF3_MARK, PORT49_FN1), - PINMUX_DATA(D4_NAF4_MARK, PORT50_FN1), - PINMUX_DATA(D5_NAF5_MARK, PORT51_FN1), - PINMUX_DATA(D6_NAF6_MARK, PORT52_FN1), - PINMUX_DATA(D7_NAF7_MARK, PORT53_FN1), - PINMUX_DATA(D8_NAF8_MARK, PORT54_FN1), - PINMUX_DATA(D9_NAF9_MARK, PORT55_FN1), - PINMUX_DATA(D10_NAF10_MARK, PORT56_FN1), - PINMUX_DATA(D11_NAF11_MARK, PORT57_FN1), - PINMUX_DATA(D12_NAF12_MARK, PORT58_FN1), - PINMUX_DATA(D13_NAF13_MARK, PORT59_FN1), - PINMUX_DATA(D14_NAF14_MARK, PORT60_FN1), - PINMUX_DATA(D15_NAF15_MARK, PORT61_FN1), - PINMUX_DATA(CS0_MARK, PORT62_FN1), - PINMUX_DATA(CS2_MARK, PORT63_FN1), - PINMUX_DATA(CS4_MARK, PORT64_FN1), - PINMUX_DATA(CS5A_MARK, PORT65_FN1), - PINMUX_DATA(CS5B_MARK, PORT66_FN1), - PINMUX_DATA(CS6A_MARK, PORT67_FN1), - PINMUX_DATA(FCE0_MARK, PORT68_FN1), - PINMUX_DATA(RD_FSC_MARK, PORT69_FN1), - PINMUX_DATA(WE0_FWE_MARK, PORT70_FN1), - PINMUX_DATA(WE1_MARK, PORT71_FN1), - PINMUX_DATA(CKO_MARK, PORT72_FN1), - PINMUX_DATA(FRB_MARK, PORT73_FN1), - PINMUX_DATA(WAIT_MARK, PORT74_FN1), - PINMUX_DATA(RDWR_MARK, PORT75_FN1), - PINMUX_DATA(MEMC_AD0_MARK, PORT76_FN1), - PINMUX_DATA(MEMC_AD1_MARK, PORT77_FN1), - PINMUX_DATA(MEMC_AD2_MARK, PORT78_FN1), - PINMUX_DATA(MEMC_AD3_MARK, PORT79_FN1), - PINMUX_DATA(MEMC_AD4_MARK, PORT80_FN1), - PINMUX_DATA(MEMC_AD5_MARK, PORT81_FN1), - PINMUX_DATA(MEMC_AD6_MARK, PORT82_FN1), - PINMUX_DATA(MEMC_AD7_MARK, PORT83_FN1), - PINMUX_DATA(MEMC_AD8_MARK, PORT84_FN1), - PINMUX_DATA(MEMC_AD9_MARK, PORT85_FN1), - PINMUX_DATA(MEMC_AD10_MARK, PORT86_FN1), - PINMUX_DATA(MEMC_AD11_MARK, PORT87_FN1), - PINMUX_DATA(MEMC_AD12_MARK, PORT88_FN1), - PINMUX_DATA(MEMC_AD13_MARK, PORT89_FN1), - PINMUX_DATA(MEMC_AD14_MARK, PORT90_FN1), - PINMUX_DATA(MEMC_AD15_MARK, PORT91_FN1), - PINMUX_DATA(MEMC_CS0_MARK, PORT92_FN1), - PINMUX_DATA(MEMC_BUSCLK_MEMC_A0_MARK, PORT93_FN1), - PINMUX_DATA(MEMC_CS1_MEMC_A1_MARK, PORT94_FN1), - PINMUX_DATA(MEMC_ADV_MEMC_DREQ0_MARK, PORT95_FN1), - PINMUX_DATA(MEMC_WAIT_MEMC_DREQ1_MARK, PORT96_FN1), - PINMUX_DATA(MEMC_NOE_MARK, PORT97_FN1), - PINMUX_DATA(MEMC_NWE_MARK, PORT98_FN1), - PINMUX_DATA(MEMC_INT_MARK, PORT99_FN1), - PINMUX_DATA(VIO_VD_MARK, PORT100_FN1), - PINMUX_DATA(VIO_HD_MARK, PORT101_FN1), - PINMUX_DATA(VIO_D0_MARK, PORT102_FN1), - PINMUX_DATA(VIO_D1_MARK, PORT103_FN1), - PINMUX_DATA(VIO_D2_MARK, PORT104_FN1), - PINMUX_DATA(VIO_D3_MARK, PORT105_FN1), - PINMUX_DATA(VIO_D4_MARK, PORT106_FN1), - PINMUX_DATA(VIO_D5_MARK, PORT107_FN1), - PINMUX_DATA(VIO_D6_MARK, PORT108_FN1), - PINMUX_DATA(VIO_D7_MARK, PORT109_FN1), - PINMUX_DATA(VIO_D8_MARK, PORT110_FN1), - PINMUX_DATA(VIO_D9_MARK, PORT111_FN1), - PINMUX_DATA(VIO_D10_MARK, PORT112_FN1), - PINMUX_DATA(VIO_D11_MARK, PORT113_FN1), - PINMUX_DATA(VIO_D12_MARK, PORT114_FN1), - PINMUX_DATA(VIO_D13_MARK, PORT115_FN1), - PINMUX_DATA(VIO_D14_MARK, PORT116_FN1), - PINMUX_DATA(VIO_D15_MARK, PORT117_FN1), - PINMUX_DATA(VIO_CLK_MARK, PORT118_FN1), - PINMUX_DATA(VIO_FIELD_MARK, PORT119_FN1), - PINMUX_DATA(VIO_CKO_MARK, PORT120_FN1), - PINMUX_DATA(LCDD0_MARK, PORT121_FN1), - PINMUX_DATA(LCDD1_MARK, PORT122_FN1), - PINMUX_DATA(LCDD2_MARK, PORT123_FN1), - PINMUX_DATA(LCDD3_MARK, PORT124_FN1), - PINMUX_DATA(LCDD4_MARK, PORT125_FN1), - PINMUX_DATA(LCDD5_MARK, PORT126_FN1), - PINMUX_DATA(LCDD6_MARK, PORT127_FN1), - PINMUX_DATA(LCDD7_MARK, PORT128_FN1), - PINMUX_DATA(LCDD8_MARK, PORT129_FN1), - PINMUX_DATA(LCDD9_MARK, PORT130_FN1), - PINMUX_DATA(LCDD10_MARK, PORT131_FN1), - PINMUX_DATA(LCDD11_MARK, PORT132_FN1), - PINMUX_DATA(LCDD12_MARK, PORT133_FN1), - PINMUX_DATA(LCDD13_MARK, PORT134_FN1), - PINMUX_DATA(LCDD14_MARK, PORT135_FN1), - PINMUX_DATA(LCDD15_MARK, PORT136_FN1), - PINMUX_DATA(LCDD16_MARK, PORT137_FN1), - PINMUX_DATA(LCDD17_MARK, PORT138_FN1), - PINMUX_DATA(LCDD18_MARK, PORT139_FN1), - PINMUX_DATA(LCDD19_MARK, PORT140_FN1), - PINMUX_DATA(LCDD20_MARK, PORT141_FN1), - PINMUX_DATA(LCDD21_MARK, PORT142_FN1), - PINMUX_DATA(LCDD22_MARK, PORT143_FN1), - PINMUX_DATA(LCDD23_MARK, PORT144_FN1), - PINMUX_DATA(LCDHSYN_MARK, PORT145_FN1), - PINMUX_DATA(LCDVSYN_MARK, PORT146_FN1), - PINMUX_DATA(LCDDCK_MARK, PORT147_FN1), - PINMUX_DATA(LCDRD_MARK, PORT148_FN1), - PINMUX_DATA(LCDDISP_MARK, PORT149_FN1), - PINMUX_DATA(LCDLCLK_MARK, PORT150_FN1), - PINMUX_DATA(LCDDON_MARK, PORT151_FN1), - PINMUX_DATA(SCIFA0_TXD_MARK, PORT152_FN1), - PINMUX_DATA(SCIFA0_RXD_MARK, PORT153_FN1), - PINMUX_DATA(SCIFA1_TXD_MARK, PORT154_FN1), - PINMUX_DATA(SCIFA1_RXD_MARK, PORT155_FN1), - PINMUX_DATA(TS_SPSYNC1_MARK, PORT156_FN1), - PINMUX_DATA(TS_SDAT1_MARK, PORT157_FN1), - PINMUX_DATA(TS_SDEN1_MARK, PORT158_FN1), - PINMUX_DATA(TS_SCK1_MARK, PORT159_FN1), - PINMUX_DATA(TPU0TO0_MARK, PORT160_FN1), - PINMUX_DATA(TPU0TO1_MARK, PORT161_FN1), - PINMUX_DATA(SCIFB_SCK_MARK, PORT162_FN1), - PINMUX_DATA(SCIFB_RTS_MARK, PORT163_FN1), - PINMUX_DATA(SCIFB_CTS_MARK, PORT164_FN1), - PINMUX_DATA(SCIFB_TXD_MARK, PORT165_FN1), - PINMUX_DATA(SCIFB_RXD_MARK, PORT166_FN1), - PINMUX_DATA(VBUS0_0_MARK, PORT167_FN1), - PINMUX_DATA(VBUS0_1_MARK, PORT168_FN1), - PINMUX_DATA(HDMI_HPD_MARK, PORT169_FN1), - PINMUX_DATA(HDMI_CEC_MARK, PORT170_FN1), - PINMUX_DATA(SDHICLK0_MARK, PORT171_FN1), - PINMUX_DATA(SDHICD0_MARK, PORT172_FN1), - PINMUX_DATA(SDHID0_0_MARK, PORT173_FN1), - PINMUX_DATA(SDHID0_1_MARK, PORT174_FN1), - PINMUX_DATA(SDHID0_2_MARK, PORT175_FN1), - PINMUX_DATA(SDHID0_3_MARK, PORT176_FN1), - PINMUX_DATA(SDHICMD0_MARK, PORT177_FN1), - PINMUX_DATA(SDHIWP0_MARK, PORT178_FN1), - PINMUX_DATA(SDHICLK1_MARK, PORT179_FN1), - PINMUX_DATA(SDHID1_0_MARK, PORT180_FN1), - PINMUX_DATA(SDHID1_1_MARK, PORT181_FN1), - PINMUX_DATA(SDHID1_2_MARK, PORT182_FN1), - PINMUX_DATA(SDHID1_3_MARK, PORT183_FN1), - PINMUX_DATA(SDHICMD1_MARK, PORT184_FN1), - PINMUX_DATA(SDHICLK2_MARK, PORT185_FN1), - PINMUX_DATA(SDHID2_0_MARK, PORT186_FN1), - PINMUX_DATA(SDHID2_1_MARK, PORT187_FN1), - PINMUX_DATA(SDHID2_2_MARK, PORT188_FN1), - PINMUX_DATA(SDHID2_3_MARK, PORT189_FN1), - PINMUX_DATA(SDHICMD2_MARK, PORT190_FN1), - - /* Function 2 */ - PINMUX_DATA(FSIBCK_MARK, PORT4_FN2), - PINMUX_DATA(SCIFA4_RXD_MARK, PORT5_FN2), - PINMUX_DATA(SCIFA4_TXD_MARK, PORT6_FN2), - PINMUX_DATA(SCIFA5_RXD_MARK, PORT8_FN2), - PINMUX_DATA(FSIASPDIF_11_MARK, PORT11_FN2), - PINMUX_DATA(SCIFA5_TXD_MARK, PORT12_FN2), - PINMUX_DATA(FMSIOLR_MARK, PORT13_FN2), - PINMUX_DATA(FMSIOBT_MARK, PORT14_FN2), - PINMUX_DATA(FSIASPDIF_15_MARK, PORT15_FN2), - PINMUX_DATA(FMSIILR_MARK, PORT16_FN2), - PINMUX_DATA(FMSIIBT_MARK, PORT17_FN2), - PINMUX_DATA(BS_MARK, PORT19_FN2), - PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT36_FN2), - PINMUX_DATA(MSIOF0_TSCK_MARK, PORT37_FN2), - PINMUX_DATA(MSIOF0_RXD_MARK, PORT38_FN2), - PINMUX_DATA(MSIOF0_RSCK_MARK, PORT39_FN2), - PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT40_FN2), - PINMUX_DATA(MSIOF0_MCK0_MARK, PORT41_FN2), - PINMUX_DATA(MSIOF0_MCK1_MARK, PORT42_FN2), - PINMUX_DATA(MSIOF0_SS1_MARK, PORT43_FN2), - PINMUX_DATA(MSIOF0_SS2_MARK, PORT44_FN2), - PINMUX_DATA(MSIOF0_TXD_MARK, PORT45_FN2), - PINMUX_DATA(FMSICK_MARK, PORT65_FN2), - PINMUX_DATA(FCE1_MARK, PORT66_FN2), - PINMUX_DATA(BBIF1_RXD_MARK, PORT76_FN2), - PINMUX_DATA(BBIF1_TSYNC_MARK, PORT77_FN2), - PINMUX_DATA(BBIF1_TSCK_MARK, PORT78_FN2), - PINMUX_DATA(BBIF1_TXD_MARK, PORT79_FN2), - PINMUX_DATA(BBIF1_RSCK_MARK, PORT80_FN2), - PINMUX_DATA(BBIF1_RSYNC_MARK, PORT81_FN2), - PINMUX_DATA(BBIF1_FLOW_MARK, PORT82_FN2), - PINMUX_DATA(BB_RX_FLOW_N_MARK, PORT83_FN2), - PINMUX_DATA(MSIOF1_RSCK_MARK, PORT84_FN2), - PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT85_FN2), - PINMUX_DATA(MSIOF1_MCK0_MARK, PORT86_FN2), - PINMUX_DATA(MSIOF1_MCK1_MARK, PORT87_FN2), - PINMUX_DATA(MSIOF1_TSCK_88_MARK, PORT88_FN2, MSEL4CR_10_1), - PINMUX_DATA(MSIOF1_TSYNC_89_MARK, PORT89_FN2, MSEL4CR_10_1), - PINMUX_DATA(MSIOF1_TXD_90_MARK, PORT90_FN2, MSEL4CR_10_1), - PINMUX_DATA(MSIOF1_RXD_91_MARK, PORT91_FN2, MSEL4CR_10_1), - PINMUX_DATA(MSIOF1_SS1_92_MARK, PORT92_FN2, MSEL4CR_10_1), - PINMUX_DATA(MSIOF1_SS2_93_MARK, PORT93_FN2, MSEL4CR_10_1), - PINMUX_DATA(SCIFA2_CTS1_MARK, PORT94_FN2), - PINMUX_DATA(SCIFA2_RTS1_MARK, PORT95_FN2), - PINMUX_DATA(SCIFA2_TXD1_MARK, PORT96_FN2), - PINMUX_DATA(SCIFA2_RXD1_MARK, PORT97_FN2), - PINMUX_DATA(SCIFA2_SCK1_MARK, PORT98_FN2), - PINMUX_DATA(I2C_SCL2_MARK, PORT110_FN2), - PINMUX_DATA(I2C_SDA2_MARK, PORT111_FN2), - PINMUX_DATA(I2C_SCL3_MARK, PORT114_FN2, MSEL4CR_16_1), - PINMUX_DATA(I2C_SDA3_MARK, PORT115_FN2, MSEL4CR_16_1), - PINMUX_DATA(I2C_SCL4_MARK, PORT116_FN2, MSEL4CR_17_1), - PINMUX_DATA(I2C_SDA4_MARK, PORT117_FN2, MSEL4CR_17_1), - PINMUX_DATA(MSIOF2_RSCK_MARK, PORT134_FN2), - PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT135_FN2), - PINMUX_DATA(MSIOF2_MCK0_MARK, PORT136_FN2), - PINMUX_DATA(MSIOF2_MCK1_MARK, PORT137_FN2), - PINMUX_DATA(MSIOF2_SS1_MARK, PORT138_FN2), - PINMUX_DATA(MSIOF2_SS2_MARK, PORT139_FN2), - PINMUX_DATA(SCIFA3_CTS_140_MARK, PORT140_FN2, MSEL3CR_9_1), - PINMUX_DATA(SCIFA3_RTS_141_MARK, PORT141_FN2), - PINMUX_DATA(SCIFA3_SCK_MARK, PORT142_FN2), - PINMUX_DATA(SCIFA3_TXD_MARK, PORT143_FN2), - PINMUX_DATA(SCIFA3_RXD_MARK, PORT144_FN2), - PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT148_FN2), - PINMUX_DATA(MSIOF2_TSCK_MARK, PORT149_FN2), - PINMUX_DATA(MSIOF2_RXD_MARK, PORT150_FN2), - PINMUX_DATA(MSIOF2_TXD_MARK, PORT151_FN2), - PINMUX_DATA(SCIFA0_SCK_MARK, PORT156_FN2), - PINMUX_DATA(SCIFA0_RTS_MARK, PORT157_FN2), - PINMUX_DATA(SCIFA0_CTS_MARK, PORT158_FN2), - PINMUX_DATA(SCIFA1_SCK_MARK, PORT159_FN2), - PINMUX_DATA(SCIFA1_RTS_MARK, PORT160_FN2), - PINMUX_DATA(SCIFA1_CTS_MARK, PORT161_FN2), - - /* Function 3 */ - PINMUX_DATA(VIO_CKO1_MARK, PORT16_FN3), - PINMUX_DATA(VIO_CKO2_MARK, PORT17_FN3), - PINMUX_DATA(IDIN_1_18_MARK, PORT18_FN3, MSEL4CR_14_1), - PINMUX_DATA(MSIOF1_TSCK_39_MARK, PORT39_FN3, MSEL4CR_10_0), - PINMUX_DATA(MSIOF1_TSYNC_40_MARK, PORT40_FN3, MSEL4CR_10_0), - PINMUX_DATA(MSIOF1_TXD_41_MARK, PORT41_FN3, MSEL4CR_10_0), - PINMUX_DATA(MSIOF1_RXD_42_MARK, PORT42_FN3, MSEL4CR_10_0), - PINMUX_DATA(MSIOF1_SS1_43_MARK, PORT43_FN3, MSEL4CR_10_0), - PINMUX_DATA(MSIOF1_SS2_44_MARK, PORT44_FN3, MSEL4CR_10_0), - PINMUX_DATA(MMCD1_0_MARK, PORT54_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMCD1_1_MARK, PORT55_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMCD1_2_MARK, PORT56_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMCD1_3_MARK, PORT57_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMCD1_4_MARK, PORT58_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMCD1_5_MARK, PORT59_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMCD1_6_MARK, PORT60_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMCD1_7_MARK, PORT61_FN3, MSEL4CR_15_1), - PINMUX_DATA(VINT_I_MARK, PORT65_FN3), - PINMUX_DATA(MMCCLK1_MARK, PORT66_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMCCMD1_MARK, PORT67_FN3, MSEL4CR_15_1), - PINMUX_DATA(TPU0TO2_93_MARK, PORT93_FN3), - PINMUX_DATA(TPU0TO2_99_MARK, PORT99_FN3), - PINMUX_DATA(TPU0TO3_MARK, PORT112_FN3), - PINMUX_DATA(IDIN_0_MARK, PORT113_FN3), - PINMUX_DATA(EXTLP_0_MARK, PORT114_FN3), - PINMUX_DATA(OVCN2_0_MARK, PORT115_FN3), - PINMUX_DATA(PWEN_0_MARK, PORT116_FN3), - PINMUX_DATA(OVCN_0_MARK, PORT117_FN3), - PINMUX_DATA(KEYOUT7_MARK, PORT121_FN3), - PINMUX_DATA(KEYOUT6_MARK, PORT122_FN3), - PINMUX_DATA(KEYOUT5_MARK, PORT123_FN3), - PINMUX_DATA(KEYOUT4_MARK, PORT124_FN3), - PINMUX_DATA(KEYOUT3_MARK, PORT125_FN3), - PINMUX_DATA(KEYOUT2_MARK, PORT126_FN3), - PINMUX_DATA(KEYOUT1_MARK, PORT127_FN3), - PINMUX_DATA(KEYOUT0_MARK, PORT128_FN3), - PINMUX_DATA(KEYIN7_MARK, PORT129_FN3), - PINMUX_DATA(KEYIN6_MARK, PORT130_FN3), - PINMUX_DATA(KEYIN5_MARK, PORT131_FN3), - PINMUX_DATA(KEYIN4_MARK, PORT132_FN3), - PINMUX_DATA(KEYIN3_133_MARK, PORT133_FN3, MSEL4CR_18_0), - PINMUX_DATA(KEYIN2_134_MARK, PORT134_FN3, MSEL4CR_18_0), - PINMUX_DATA(KEYIN1_135_MARK, PORT135_FN3, MSEL4CR_18_0), - PINMUX_DATA(KEYIN0_136_MARK, PORT136_FN3, MSEL4CR_18_0), - PINMUX_DATA(TS_SPSYNC2_MARK, PORT137_FN3), - PINMUX_DATA(IROUT_139_MARK, PORT139_FN3), - PINMUX_DATA(IRDA_OUT_MARK, PORT140_FN3), - PINMUX_DATA(IRDA_IN_MARK, PORT141_FN3), - PINMUX_DATA(IRDA_FIRSEL_MARK, PORT142_FN3), - PINMUX_DATA(TS_SDAT2_MARK, PORT145_FN3), - PINMUX_DATA(TS_SDEN2_MARK, PORT146_FN3), - PINMUX_DATA(TS_SCK2_MARK, PORT147_FN3), - - /* Function 4 */ - PINMUX_DATA(SCIFA3_CTS_43_MARK, PORT43_FN4, MSEL3CR_9_0), - PINMUX_DATA(SCIFA3_RTS_44_MARK, PORT44_FN4), - PINMUX_DATA(GP_RX_FLAG_MARK, PORT76_FN4), - PINMUX_DATA(GP_RX_DATA_MARK, PORT77_FN4), - PINMUX_DATA(GP_TX_READY_MARK, PORT78_FN4), - PINMUX_DATA(GP_RX_WAKE_MARK, PORT79_FN4), - PINMUX_DATA(MP_TX_FLAG_MARK, PORT80_FN4), - PINMUX_DATA(MP_TX_DATA_MARK, PORT81_FN4), - PINMUX_DATA(MP_RX_READY_MARK, PORT82_FN4), - PINMUX_DATA(MP_TX_WAKE_MARK, PORT83_FN4), - PINMUX_DATA(MMCD0_0_MARK, PORT84_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMCD0_1_MARK, PORT85_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMCD0_2_MARK, PORT86_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMCD0_3_MARK, PORT87_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMCD0_4_MARK, PORT88_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMCD0_5_MARK, PORT89_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMCD0_6_MARK, PORT90_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMCD0_7_MARK, PORT91_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMCCMD0_MARK, PORT92_FN4, MSEL4CR_15_0), - PINMUX_DATA(SIM_RST_MARK, PORT94_FN4), - PINMUX_DATA(SIM_CLK_MARK, PORT95_FN4), - PINMUX_DATA(SIM_D_MARK, PORT98_FN4), - PINMUX_DATA(MMCCLK0_MARK, PORT99_FN4, MSEL4CR_15_0), - PINMUX_DATA(IDIN_1_113_MARK, PORT113_FN4, MSEL4CR_14_0), - PINMUX_DATA(OVCN_1_114_MARK, PORT114_FN4, MSEL4CR_14_0), - PINMUX_DATA(PWEN_1_115_MARK, PORT115_FN4), - PINMUX_DATA(EXTLP_1_MARK, PORT116_FN4), - PINMUX_DATA(OVCN2_1_MARK, PORT117_FN4), - PINMUX_DATA(KEYIN0_121_MARK, PORT121_FN4, MSEL4CR_18_1), - PINMUX_DATA(KEYIN1_122_MARK, PORT122_FN4, MSEL4CR_18_1), - PINMUX_DATA(KEYIN2_123_MARK, PORT123_FN4, MSEL4CR_18_1), - PINMUX_DATA(KEYIN3_124_MARK, PORT124_FN4, MSEL4CR_18_1), - PINMUX_DATA(PWEN_1_138_MARK, PORT138_FN4), - PINMUX_DATA(IROUT_140_MARK, PORT140_FN4), - PINMUX_DATA(LCDCS_MARK, PORT145_FN4), - PINMUX_DATA(LCDWR_MARK, PORT147_FN4), - PINMUX_DATA(LCDRS_MARK, PORT149_FN4), - PINMUX_DATA(OVCN_1_162_MARK, PORT162_FN4, MSEL4CR_14_1), - - /* Function 5 */ - PINMUX_DATA(GPI0_MARK, PORT41_FN5), - PINMUX_DATA(GPI1_MARK, PORT42_FN5), - PINMUX_DATA(GPO0_MARK, PORT43_FN5), - PINMUX_DATA(GPO1_MARK, PORT44_FN5), - PINMUX_DATA(I2C_SCL3S_MARK, PORT137_FN5, MSEL4CR_16_0), - PINMUX_DATA(I2C_SDA3S_MARK, PORT145_FN5, MSEL4CR_16_0), - PINMUX_DATA(I2C_SCL4S_MARK, PORT146_FN5, MSEL4CR_17_0), - PINMUX_DATA(I2C_SDA4S_MARK, PORT147_FN5, MSEL4CR_17_0), - - /* Function select */ - PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0), - PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1), - - PINMUX_DATA(TS0_1SELECT_MARK, MSEL3CR_21_0, MSEL3CR_20_0), - PINMUX_DATA(TS0_2SELECT_MARK, MSEL3CR_21_0, MSEL3CR_20_1), - PINMUX_DATA(TS1_1SELECT_MARK, MSEL3CR_27_0, MSEL3CR_26_0), - PINMUX_DATA(TS1_2SELECT_MARK, MSEL3CR_27_0, MSEL3CR_26_1), - - PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0), - PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1), - - PINMUX_DATA(MFIv6_MARK, MSEL4CR_6_0), - PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), -}; - -#define __I (SH_PFC_PIN_CFG_INPUT) -#define __O (SH_PFC_PIN_CFG_OUTPUT) -#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) -#define __PD (SH_PFC_PIN_CFG_PULL_DOWN) -#define __PU (SH_PFC_PIN_CFG_PULL_UP) -#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) - -#define SH7372_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD) -#define SH7372_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU) -#define SH7372_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD) -#define SH7372_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO) -#define SH7372_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD) -#define SH7372_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU) -#define SH7372_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) -#define SH7372_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) -#define SH7372_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD) - -static const struct sh_pfc_pin pinmux_pins[] = { - /* Table 57-1 (I/O and Pull U/D) */ - SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1), - SH7372_PIN_O(2), SH7372_PIN_I_PD(3), - SH7372_PIN_I_PD(4), SH7372_PIN_I_PD(5), - SH7372_PIN_IO_PU_PD(6), SH7372_PIN_I_PD(7), - SH7372_PIN_IO_PD(8), SH7372_PIN_O(9), - SH7372_PIN_O(10), SH7372_PIN_O(11), - SH7372_PIN_IO_PU_PD(12), SH7372_PIN_IO_PD(13), - SH7372_PIN_IO_PD(14), SH7372_PIN_O(15), - SH7372_PIN_IO_PD(16), SH7372_PIN_IO_PD(17), - SH7372_PIN_I_PD(18), SH7372_PIN_IO(19), - SH7372_PIN_IO(20), SH7372_PIN_IO(21), - SH7372_PIN_IO(22), SH7372_PIN_IO(23), - SH7372_PIN_IO(24), SH7372_PIN_IO(25), - SH7372_PIN_IO(26), SH7372_PIN_IO(27), - SH7372_PIN_IO(28), SH7372_PIN_IO(29), - SH7372_PIN_IO(30), SH7372_PIN_IO(31), - SH7372_PIN_IO(32), SH7372_PIN_IO(33), - SH7372_PIN_IO(34), SH7372_PIN_IO(35), - SH7372_PIN_IO(36), SH7372_PIN_IO(37), - SH7372_PIN_IO(38), SH7372_PIN_IO(39), - SH7372_PIN_IO(40), SH7372_PIN_IO(41), - SH7372_PIN_IO(42), SH7372_PIN_IO(43), - SH7372_PIN_IO(44), SH7372_PIN_IO(45), - SH7372_PIN_IO_PU(46), SH7372_PIN_IO_PU(47), - SH7372_PIN_IO_PU(48), SH7372_PIN_IO_PU(49), - SH7372_PIN_IO_PU(50), SH7372_PIN_IO_PU(51), - SH7372_PIN_IO_PU(52), SH7372_PIN_IO_PU(53), - SH7372_PIN_IO_PU(54), SH7372_PIN_IO_PU(55), - SH7372_PIN_IO_PU(56), SH7372_PIN_IO_PU(57), - SH7372_PIN_IO_PU(58), SH7372_PIN_IO_PU(59), - SH7372_PIN_IO_PU(60), SH7372_PIN_IO_PU(61), - SH7372_PIN_IO(62), SH7372_PIN_O(63), - SH7372_PIN_O(64), SH7372_PIN_IO_PU(65), - SH7372_PIN_O_PU_PD(66), SH7372_PIN_IO_PU(67), - SH7372_PIN_O(68), SH7372_PIN_IO(69), - SH7372_PIN_IO(70), SH7372_PIN_IO(71), - SH7372_PIN_O(72), SH7372_PIN_I_PU(73), - SH7372_PIN_I_PU_PD(74), SH7372_PIN_IO_PU_PD(75), - SH7372_PIN_IO_PU_PD(76), SH7372_PIN_IO_PU_PD(77), - SH7372_PIN_IO_PU_PD(78), SH7372_PIN_IO_PU_PD(79), - SH7372_PIN_IO_PU_PD(80), SH7372_PIN_IO_PU_PD(81), - SH7372_PIN_IO_PU_PD(82), SH7372_PIN_IO_PU_PD(83), - SH7372_PIN_IO_PU_PD(84), SH7372_PIN_IO_PU_PD(85), - SH7372_PIN_IO_PU_PD(86), SH7372_PIN_IO_PU_PD(87), - SH7372_PIN_IO_PU_PD(88), SH7372_PIN_IO_PU_PD(89), - SH7372_PIN_IO_PU_PD(90), SH7372_PIN_IO_PU_PD(91), - SH7372_PIN_IO_PU_PD(92), SH7372_PIN_IO_PU_PD(93), - SH7372_PIN_IO_PU_PD(94), SH7372_PIN_IO_PU_PD(95), - SH7372_PIN_IO_PU(96), SH7372_PIN_IO_PU_PD(97), - SH7372_PIN_IO_PU_PD(98), SH7372_PIN_O_PU_PD(99), - SH7372_PIN_IO_PD(100), SH7372_PIN_IO_PD(101), - SH7372_PIN_IO_PD(102), SH7372_PIN_IO_PD(103), - SH7372_PIN_IO_PD(104), SH7372_PIN_IO_PD(105), - SH7372_PIN_IO_PU(106), SH7372_PIN_IO_PU(107), - SH7372_PIN_IO_PU(108), SH7372_PIN_IO_PU(109), - SH7372_PIN_IO_PU(110), SH7372_PIN_IO_PU(111), - SH7372_PIN_IO_PD(112), SH7372_PIN_IO_PD(113), - SH7372_PIN_IO_PU(114), SH7372_PIN_IO_PU(115), - SH7372_PIN_IO_PU(116), SH7372_PIN_IO_PU(117), - SH7372_PIN_IO_PU(118), SH7372_PIN_IO_PU(119), - SH7372_PIN_IO_PU(120), SH7372_PIN_IO_PD(121), - SH7372_PIN_IO_PD(122), SH7372_PIN_IO_PD(123), - SH7372_PIN_IO_PD(124), SH7372_PIN_IO_PD(125), - SH7372_PIN_IO_PD(126), SH7372_PIN_IO_PD(127), - SH7372_PIN_IO_PD(128), SH7372_PIN_IO_PU_PD(129), - SH7372_PIN_IO_PU_PD(130), SH7372_PIN_IO_PU_PD(131), - SH7372_PIN_IO_PU_PD(132), SH7372_PIN_IO_PU_PD(133), - SH7372_PIN_IO_PU_PD(134), SH7372_PIN_IO_PU_PD(135), - SH7372_PIN_IO_PD(136), SH7372_PIN_IO_PD(137), - SH7372_PIN_IO_PD(138), SH7372_PIN_IO_PD(139), - SH7372_PIN_IO_PD(140), SH7372_PIN_IO_PD(141), - SH7372_PIN_IO_PD(142), SH7372_PIN_IO_PU_PD(143), - SH7372_PIN_IO_PD(144), SH7372_PIN_IO_PD(145), - SH7372_PIN_IO_PD(146), SH7372_PIN_IO_PD(147), - SH7372_PIN_IO_PD(148), SH7372_PIN_IO_PD(149), - SH7372_PIN_IO_PD(150), SH7372_PIN_IO_PD(151), - SH7372_PIN_IO_PU_PD(152), SH7372_PIN_I_PD(153), - SH7372_PIN_IO_PU_PD(154), SH7372_PIN_I_PD(155), - SH7372_PIN_IO_PD(156), SH7372_PIN_IO_PD(157), - SH7372_PIN_I_PD(158), SH7372_PIN_IO_PD(159), - SH7372_PIN_O(160), SH7372_PIN_IO_PD(161), - SH7372_PIN_IO_PD(162), SH7372_PIN_IO_PD(163), - SH7372_PIN_I_PD(164), SH7372_PIN_IO_PD(165), - SH7372_PIN_I_PD(166), SH7372_PIN_I_PD(167), - SH7372_PIN_I_PD(168), SH7372_PIN_I_PD(169), - SH7372_PIN_I_PD(170), SH7372_PIN_O(171), - SH7372_PIN_IO_PU_PD(172), SH7372_PIN_IO_PU_PD(173), - SH7372_PIN_IO_PU_PD(174), SH7372_PIN_IO_PU_PD(175), - SH7372_PIN_IO_PU_PD(176), SH7372_PIN_IO_PU_PD(177), - SH7372_PIN_IO_PU_PD(178), SH7372_PIN_O(179), - SH7372_PIN_IO_PU_PD(180), SH7372_PIN_IO_PU_PD(181), - SH7372_PIN_IO_PU_PD(182), SH7372_PIN_IO_PU_PD(183), - SH7372_PIN_IO_PU_PD(184), SH7372_PIN_O(185), - SH7372_PIN_IO_PU_PD(186), SH7372_PIN_IO_PU_PD(187), - SH7372_PIN_IO_PU_PD(188), SH7372_PIN_IO_PU_PD(189), - SH7372_PIN_IO_PU_PD(190), -}; - -/* - BSC -------------------------------------------------------------------- */ -static const unsigned int bsc_data8_pins[] = { - /* D[0:7] */ - 46, 47, 48, 49, 50, 51, 52, 53, -}; -static const unsigned int bsc_data8_mux[] = { - D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, - D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, -}; -static const unsigned int bsc_data16_pins[] = { - /* D[0:15] */ - 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, -}; -static const unsigned int bsc_data16_mux[] = { - D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, - D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, - D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, - D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, -}; -static const unsigned int bsc_cs0_pins[] = { - /* CS */ - 62, -}; -static const unsigned int bsc_cs0_mux[] = { - CS0_MARK, -}; -static const unsigned int bsc_cs2_pins[] = { - /* CS */ - 63, -}; -static const unsigned int bsc_cs2_mux[] = { - CS2_MARK, -}; -static const unsigned int bsc_cs4_pins[] = { - /* CS */ - 64, -}; -static const unsigned int bsc_cs4_mux[] = { - CS4_MARK, -}; -static const unsigned int bsc_cs5a_pins[] = { - /* CS */ - 65, -}; -static const unsigned int bsc_cs5a_mux[] = { - CS5A_MARK, -}; -static const unsigned int bsc_cs5b_pins[] = { - /* CS */ - 66, -}; -static const unsigned int bsc_cs5b_mux[] = { - CS5B_MARK, -}; -static const unsigned int bsc_cs6a_pins[] = { - /* CS */ - 67, -}; -static const unsigned int bsc_cs6a_mux[] = { - CS6A_MARK, -}; -static const unsigned int bsc_rd_we8_pins[] = { - /* RD, WE[0] */ - 69, 70, -}; -static const unsigned int bsc_rd_we8_mux[] = { - RD_FSC_MARK, WE0_FWE_MARK, -}; -static const unsigned int bsc_rd_we16_pins[] = { - /* RD, WE[0:1] */ - 69, 70, 71, -}; -static const unsigned int bsc_rd_we16_mux[] = { - RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, -}; -static const unsigned int bsc_bs_pins[] = { - /* BS */ - 19, -}; -static const unsigned int bsc_bs_mux[] = { - BS_MARK, -}; -static const unsigned int bsc_rdwr_pins[] = { - /* RDWR */ - 75, -}; -static const unsigned int bsc_rdwr_mux[] = { - RDWR_MARK, -}; -static const unsigned int bsc_wait_pins[] = { - /* WAIT */ - 74, -}; -static const unsigned int bsc_wait_mux[] = { - WAIT_MARK, -}; -/* - CEU -------------------------------------------------------------------- */ -static const unsigned int ceu_data_0_7_pins[] = { - /* D[0:7] */ - 102, 103, 104, 105, 106, 107, 108, 109, -}; -static const unsigned int ceu_data_0_7_mux[] = { - VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK, - VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK, -}; -static const unsigned int ceu_data_8_15_pins[] = { - /* D[8:15] */ - 110, 111, 112, 113, 114, 115, 116, 117, -}; -static const unsigned int ceu_data_8_15_mux[] = { - VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK, - VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK, -}; -static const unsigned int ceu_clk_0_pins[] = { - /* CKO */ - 120, -}; -static const unsigned int ceu_clk_0_mux[] = { - VIO_CKO_MARK, -}; -static const unsigned int ceu_clk_1_pins[] = { - /* CKO */ - 16, -}; -static const unsigned int ceu_clk_1_mux[] = { - VIO_CKO1_MARK, -}; -static const unsigned int ceu_clk_2_pins[] = { - /* CKO */ - 17, -}; -static const unsigned int ceu_clk_2_mux[] = { - VIO_CKO2_MARK, -}; -static const unsigned int ceu_sync_pins[] = { - /* CLK, VD, HD */ - 118, 100, 101, -}; -static const unsigned int ceu_sync_mux[] = { - VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK, -}; -static const unsigned int ceu_field_pins[] = { - /* FIELD */ - 119, -}; -static const unsigned int ceu_field_mux[] = { - VIO_FIELD_MARK, -}; -/* - FLCTL ------------------------------------------------------------------ */ -static const unsigned int flctl_data_pins[] = { - /* NAF[0:15] */ - 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, -}; -static const unsigned int flctl_data_mux[] = { - D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, - D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, - D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, - D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, -}; -static const unsigned int flctl_ce0_pins[] = { - /* CE */ - 68, -}; -static const unsigned int flctl_ce0_mux[] = { - FCE0_MARK, -}; -static const unsigned int flctl_ce1_pins[] = { - /* CE */ - 66, -}; -static const unsigned int flctl_ce1_mux[] = { - FCE1_MARK, -}; -static const unsigned int flctl_ctrl_pins[] = { - /* FCDE, FOE, FSC, FWE, FRB */ - 24, 23, 69, 70, 73, -}; -static const unsigned int flctl_ctrl_mux[] = { - A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK, -}; -/* - FSIA ------------------------------------------------------------------- */ -static const unsigned int fsia_mclk_in_pins[] = { - /* CK */ - 4, -}; -static const unsigned int fsia_mclk_in_mux[] = { - FSIACK_MARK, -}; -static const unsigned int fsia_mclk_out_pins[] = { - /* OMC */ - 8, -}; -static const unsigned int fsia_mclk_out_mux[] = { - FSIAOMC_MARK, -}; -static const unsigned int fsia_sclk_in_pins[] = { - /* ILR, IBT */ - 5, 6, -}; -static const unsigned int fsia_sclk_in_mux[] = { - FSIAILR_MARK, FSIAIBT_MARK, -}; -static const unsigned int fsia_sclk_out_pins[] = { - /* OLR, OBT */ - 9, 10, -}; -static const unsigned int fsia_sclk_out_mux[] = { - FSIAOLR_MARK, FSIAOBT_MARK, -}; -static const unsigned int fsia_data_in_pins[] = { - /* ISLD */ - 7, -}; -static const unsigned int fsia_data_in_mux[] = { - FSIAISLD_MARK, -}; -static const unsigned int fsia_data_out_pins[] = { - /* OSLD */ - 11, -}; -static const unsigned int fsia_data_out_mux[] = { - FSIAOSLD_MARK, -}; -static const unsigned int fsia_spdif_0_pins[] = { - /* SPDIF */ - 11, -}; -static const unsigned int fsia_spdif_0_mux[] = { - FSIASPDIF_11_MARK, -}; -static const unsigned int fsia_spdif_1_pins[] = { - /* SPDIF */ - 15, -}; -static const unsigned int fsia_spdif_1_mux[] = { - FSIASPDIF_15_MARK, -}; -/* - FSIB ------------------------------------------------------------------- */ -static const unsigned int fsib_mclk_in_pins[] = { - /* CK */ - 4, -}; -static const unsigned int fsib_mclk_in_mux[] = { - FSIBCK_MARK, -}; -/* - HDMI ------------------------------------------------------------------- */ -static const unsigned int hdmi_pins[] = { - /* HPD, CEC */ - 169, 170, -}; -static const unsigned int hdmi_mux[] = { - HDMI_HPD_MARK, HDMI_CEC_MARK, -}; -/* - INTC ------------------------------------------------------------------- */ -IRQC_PINS_MUX(0, 6, 162); -IRQC_PIN_MUX(1, 12); -IRQC_PINS_MUX(2, 4, 5); -IRQC_PINS_MUX(3, 8, 16); -IRQC_PINS_MUX(4, 17, 163); -IRQC_PIN_MUX(5, 18); -IRQC_PINS_MUX(6, 39, 164); -IRQC_PINS_MUX(7, 40, 167); -IRQC_PINS_MUX(8, 41, 168); -IRQC_PINS_MUX(9, 42, 169); -IRQC_PIN_MUX(10, 65); -IRQC_PIN_MUX(11, 67); -IRQC_PINS_MUX(12, 80, 137); -IRQC_PINS_MUX(13, 81, 145); -IRQC_PINS_MUX(14, 82, 146); -IRQC_PINS_MUX(15, 83, 147); -IRQC_PINS_MUX(16, 84, 170); -IRQC_PIN_MUX(17, 85); -IRQC_PIN_MUX(18, 86); -IRQC_PIN_MUX(19, 87); -IRQC_PIN_MUX(20, 92); -IRQC_PIN_MUX(21, 93); -IRQC_PIN_MUX(22, 94); -IRQC_PIN_MUX(23, 95); -IRQC_PIN_MUX(24, 112); -IRQC_PIN_MUX(25, 119); -IRQC_PINS_MUX(26, 121, 172); -IRQC_PINS_MUX(27, 122, 180); -IRQC_PINS_MUX(28, 123, 181); -IRQC_PINS_MUX(29, 129, 182); -IRQC_PINS_MUX(30, 130, 183); -IRQC_PINS_MUX(31, 138, 184); -/* - KEYSC ------------------------------------------------------------------ */ -static const unsigned int keysc_in04_0_pins[] = { - /* KEYIN[0:4] */ - 136, 135, 134, 133, 132, -}; -static const unsigned int keysc_in04_0_mux[] = { - KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK, - KEYIN4_MARK, -}; -static const unsigned int keysc_in04_1_pins[] = { - /* KEYIN[0:4] */ - 121, 122, 123, 124, 132, -}; -static const unsigned int keysc_in04_1_mux[] = { - KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK, - KEYIN4_MARK, -}; -static const unsigned int keysc_in5_pins[] = { - /* KEYIN5 */ - 131, -}; -static const unsigned int keysc_in5_mux[] = { - KEYIN5_MARK, -}; -static const unsigned int keysc_in6_pins[] = { - /* KEYIN6 */ - 130, -}; -static const unsigned int keysc_in6_mux[] = { - KEYIN6_MARK, -}; -static const unsigned int keysc_in7_pins[] = { - /* KEYIN7 */ - 129, -}; -static const unsigned int keysc_in7_mux[] = { - KEYIN7_MARK, -}; -static const unsigned int keysc_out4_pins[] = { - /* KEYOUT[0:3] */ - 128, 127, 126, 125, -}; -static const unsigned int keysc_out4_mux[] = { - KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, -}; -static const unsigned int keysc_out5_pins[] = { - /* KEYOUT[0:4] */ - 128, 127, 126, 125, 124, -}; -static const unsigned int keysc_out5_mux[] = { - KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, - KEYOUT4_MARK, -}; -static const unsigned int keysc_out6_pins[] = { - /* KEYOUT[0:5] */ - 128, 127, 126, 125, 124, 123, -}; -static const unsigned int keysc_out6_mux[] = { - KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, - KEYOUT4_MARK, KEYOUT5_MARK, -}; -static const unsigned int keysc_out8_pins[] = { - /* KEYOUT[0:7] */ - 128, 127, 126, 125, 124, 123, 122, 121, -}; -static const unsigned int keysc_out8_mux[] = { - KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, - KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK, -}; -/* - LCD -------------------------------------------------------------------- */ -static const unsigned int lcd_data8_pins[] = { - /* D[0:7] */ - 121, 122, 123, 124, 125, 126, 127, 128, -}; -static const unsigned int lcd_data8_mux[] = { - /* LCDC */ - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, -}; -static const unsigned int lcd_data9_pins[] = { - /* D[0:8] */ - 121, 122, 123, 124, 125, 126, 127, 128, - 129, - 137, 138, 139, 140, 141, 142, 143, 144, -}; -static const unsigned int lcd_data9_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, -}; -static const unsigned int lcd_data12_pins[] = { - /* D[0:11] */ - 121, 122, 123, 124, 125, 126, 127, 128, - 129, 130, 131, 132, -}; -static const unsigned int lcd_data12_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, -}; -static const unsigned int lcd_data16_pins[] = { - /* D[0:15] */ - 121, 122, 123, 124, 125, 126, 127, 128, - 129, 130, 131, 132, 133, 134, 135, 136, -}; -static const unsigned int lcd_data16_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, - LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, -}; -static const unsigned int lcd_data18_pins[] = { - /* D[0:17] */ - 121, 122, 123, 124, 125, 126, 127, 128, - 129, 130, 131, 132, 133, 134, 135, 136, - 137, 138, -}; -static const unsigned int lcd_data18_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, - LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, - LCDD16_MARK, LCDD17_MARK, -}; -static const unsigned int lcd_data24_pins[] = { - /* D[0:23] */ - 121, 122, 123, 124, 125, 126, 127, 128, - 129, 130, 131, 132, 133, 134, 135, 136, - 137, 138, 139, 140, 141, 142, 143, 144, -}; -static const unsigned int lcd_data24_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, - LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, - LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK, - LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK, -}; -static const unsigned int lcd_display_pins[] = { - /* DON */ - 151, -}; -static const unsigned int lcd_display_mux[] = { - LCDDON_MARK, -}; -static const unsigned int lcd_lclk_pins[] = { - /* LCLK */ - 150, -}; -static const unsigned int lcd_lclk_mux[] = { - LCDLCLK_MARK, -}; -static const unsigned int lcd_sync_pins[] = { - /* VSYN, HSYN, DCK, DISP */ - 146, 145, 147, 149, -}; -static const unsigned int lcd_sync_mux[] = { - LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK, -}; -static const unsigned int lcd_sys_pins[] = { - /* CS, WR, RD, RS */ - 145, 147, 148, 149, -}; -static const unsigned int lcd_sys_mux[] = { - LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK, -}; -/* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc0_data1_0_pins[] = { - /* D[0] */ - 84, -}; -static const unsigned int mmc0_data1_0_mux[] = { - MMCD0_0_MARK, -}; -static const unsigned int mmc0_data4_0_pins[] = { - /* D[0:3] */ - 84, 85, 86, 87, -}; -static const unsigned int mmc0_data4_0_mux[] = { - MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, -}; -static const unsigned int mmc0_data8_0_pins[] = { - /* D[0:7] */ - 84, 85, 86, 87, 88, 89, 90, 91, -}; -static const unsigned int mmc0_data8_0_mux[] = { - MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, - MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, -}; -static const unsigned int mmc0_ctrl_0_pins[] = { - /* CMD, CLK */ - 92, 99, -}; -static const unsigned int mmc0_ctrl_0_mux[] = { - MMCCMD0_MARK, MMCCLK0_MARK, -}; - -static const unsigned int mmc0_data1_1_pins[] = { - /* D[0] */ - 54, -}; -static const unsigned int mmc0_data1_1_mux[] = { - MMCD1_0_MARK, -}; -static const unsigned int mmc0_data4_1_pins[] = { - /* D[0:3] */ - 54, 55, 56, 57, -}; -static const unsigned int mmc0_data4_1_mux[] = { - MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, -}; -static const unsigned int mmc0_data8_1_pins[] = { - /* D[0:7] */ - 54, 55, 56, 57, 58, 59, 60, 61, -}; -static const unsigned int mmc0_data8_1_mux[] = { - MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, - MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, -}; -static const unsigned int mmc0_ctrl_1_pins[] = { - /* CMD, CLK */ - 67, 66, -}; -static const unsigned int mmc0_ctrl_1_mux[] = { - MMCCMD1_MARK, MMCCLK1_MARK, -}; -/* - SCIFA0 ----------------------------------------------------------------- */ -static const unsigned int scifa0_data_pins[] = { - /* RXD, TXD */ - 153, 152, -}; -static const unsigned int scifa0_data_mux[] = { - SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, -}; -static const unsigned int scifa0_clk_pins[] = { - /* SCK */ - 156, -}; -static const unsigned int scifa0_clk_mux[] = { - SCIFA0_SCK_MARK, -}; -static const unsigned int scifa0_ctrl_pins[] = { - /* RTS, CTS */ - 157, 158, -}; -static const unsigned int scifa0_ctrl_mux[] = { - SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, -}; -/* - SCIFA1 ----------------------------------------------------------------- */ -static const unsigned int scifa1_data_pins[] = { - /* RXD, TXD */ - 155, 154, -}; -static const unsigned int scifa1_data_mux[] = { - SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, -}; -static const unsigned int scifa1_clk_pins[] = { - /* SCK */ - 159, -}; -static const unsigned int scifa1_clk_mux[] = { - SCIFA1_SCK_MARK, -}; -static const unsigned int scifa1_ctrl_pins[] = { - /* RTS, CTS */ - 160, 161, -}; -static const unsigned int scifa1_ctrl_mux[] = { - SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, -}; -/* - SCIFA2 ----------------------------------------------------------------- */ -static const unsigned int scifa2_data_pins[] = { - /* RXD, TXD */ - 97, 96, -}; -static const unsigned int scifa2_data_mux[] = { - SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK, -}; -static const unsigned int scifa2_clk_pins[] = { - /* SCK */ - 98, -}; -static const unsigned int scifa2_clk_mux[] = { - SCIFA2_SCK1_MARK, -}; -static const unsigned int scifa2_ctrl_pins[] = { - /* RTS, CTS */ - 95, 94, -}; -static const unsigned int scifa2_ctrl_mux[] = { - SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK, -}; -/* - SCIFA3 ----------------------------------------------------------------- */ -static const unsigned int scifa3_data_pins[] = { - /* RXD, TXD */ - 144, 143, -}; -static const unsigned int scifa3_data_mux[] = { - SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, -}; -static const unsigned int scifa3_clk_pins[] = { - /* SCK */ - 142, -}; -static const unsigned int scifa3_clk_mux[] = { - SCIFA3_SCK_MARK, -}; -static const unsigned int scifa3_ctrl_0_pins[] = { - /* RTS, CTS */ - 44, 43, -}; -static const unsigned int scifa3_ctrl_0_mux[] = { - SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK, -}; -static const unsigned int scifa3_ctrl_1_pins[] = { - /* RTS, CTS */ - 141, 140, -}; -static const unsigned int scifa3_ctrl_1_mux[] = { - SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK, -}; -/* - SCIFA4 ----------------------------------------------------------------- */ -static const unsigned int scifa4_data_pins[] = { - /* RXD, TXD */ - 5, 6, -}; -static const unsigned int scifa4_data_mux[] = { - SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, -}; -/* - SCIFA5 ----------------------------------------------------------------- */ -static const unsigned int scifa5_data_pins[] = { - /* RXD, TXD */ - 8, 12, -}; -static const unsigned int scifa5_data_mux[] = { - SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, -}; -/* - SCIFB ------------------------------------------------------------------ */ -static const unsigned int scifb_data_pins[] = { - /* RXD, TXD */ - 166, 165, -}; -static const unsigned int scifb_data_mux[] = { - SCIFB_RXD_MARK, SCIFB_TXD_MARK, -}; -static const unsigned int scifb_clk_pins[] = { - /* SCK */ - 162, -}; -static const unsigned int scifb_clk_mux[] = { - SCIFB_SCK_MARK, -}; -static const unsigned int scifb_ctrl_pins[] = { - /* RTS, CTS */ - 163, 164, -}; -static const unsigned int scifb_ctrl_mux[] = { - SCIFB_RTS_MARK, SCIFB_CTS_MARK, -}; -/* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - 173, -}; -static const unsigned int sdhi0_data1_mux[] = { - SDHID0_0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { - /* D[0:3] */ - 173, 174, 175, 176, -}; -static const unsigned int sdhi0_data4_mux[] = { - SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, -}; -static const unsigned int sdhi0_ctrl_pins[] = { - /* CMD, CLK */ - 177, 171, -}; -static const unsigned int sdhi0_ctrl_mux[] = { - SDHICMD0_MARK, SDHICLK0_MARK, -}; -static const unsigned int sdhi0_cd_pins[] = { - /* CD */ - 172, -}; -static const unsigned int sdhi0_cd_mux[] = { - SDHICD0_MARK, -}; -static const unsigned int sdhi0_wp_pins[] = { - /* WP */ - 178, -}; -static const unsigned int sdhi0_wp_mux[] = { - SDHIWP0_MARK, -}; -/* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - 180, -}; -static const unsigned int sdhi1_data1_mux[] = { - SDHID1_0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { - /* D[0:3] */ - 180, 181, 182, 183, -}; -static const unsigned int sdhi1_data4_mux[] = { - SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, -}; -static const unsigned int sdhi1_ctrl_pins[] = { - /* CMD, CLK */ - 184, 179, -}; -static const unsigned int sdhi1_ctrl_mux[] = { - SDHICMD1_MARK, SDHICLK1_MARK, -}; - -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - 186, -}; -static const unsigned int sdhi2_data1_mux[] = { - SDHID2_0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - 186, 187, 188, 189, -}; -static const unsigned int sdhi2_data4_mux[] = { - SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, -}; -static const unsigned int sdhi2_ctrl_pins[] = { - /* CMD, CLK */ - 190, 185, -}; -static const unsigned int sdhi2_ctrl_mux[] = { - SDHICMD2_MARK, SDHICLK2_MARK, -}; -/* - USB0 ------------------------------------------------------------------- */ -static const unsigned int usb0_vbus_pins[] = { - /* VBUS */ - 167, -}; -static const unsigned int usb0_vbus_mux[] = { - VBUS0_0_MARK, -}; -static const unsigned int usb0_otg_id_pins[] = { - /* IDIN */ - 113, -}; -static const unsigned int usb0_otg_id_mux[] = { - IDIN_0_MARK, -}; -static const unsigned int usb0_otg_ctrl_pins[] = { - /* PWEN, EXTLP, OVCN, OVCN2 */ - 116, 114, 117, 115, -}; -static const unsigned int usb0_otg_ctrl_mux[] = { - PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK, -}; -/* - USB1 ------------------------------------------------------------------- */ -static const unsigned int usb1_vbus_pins[] = { - /* VBUS */ - 168, -}; -static const unsigned int usb1_vbus_mux[] = { - VBUS0_1_MARK, -}; -static const unsigned int usb1_otg_id_0_pins[] = { - /* IDIN */ - 113, -}; -static const unsigned int usb1_otg_id_0_mux[] = { - IDIN_1_113_MARK, -}; -static const unsigned int usb1_otg_id_1_pins[] = { - /* IDIN */ - 18, -}; -static const unsigned int usb1_otg_id_1_mux[] = { - IDIN_1_18_MARK, -}; -static const unsigned int usb1_otg_ctrl_0_pins[] = { - /* PWEN, EXTLP, OVCN, OVCN2 */ - 115, 116, 114, 117, 113, -}; -static const unsigned int usb1_otg_ctrl_0_mux[] = { - PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK, -}; -static const unsigned int usb1_otg_ctrl_1_pins[] = { - /* PWEN, EXTLP, OVCN, OVCN2 */ - 138, 116, 162, 117, 18, -}; -static const unsigned int usb1_otg_ctrl_1_mux[] = { - PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK, -}; - -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(bsc_data8), - SH_PFC_PIN_GROUP(bsc_data16), - SH_PFC_PIN_GROUP(bsc_cs0), - SH_PFC_PIN_GROUP(bsc_cs2), - SH_PFC_PIN_GROUP(bsc_cs4), - SH_PFC_PIN_GROUP(bsc_cs5a), - SH_PFC_PIN_GROUP(bsc_cs5b), - SH_PFC_PIN_GROUP(bsc_cs6a), - SH_PFC_PIN_GROUP(bsc_rd_we8), - SH_PFC_PIN_GROUP(bsc_rd_we16), - SH_PFC_PIN_GROUP(bsc_bs), - SH_PFC_PIN_GROUP(bsc_rdwr), - SH_PFC_PIN_GROUP(ceu_data_0_7), - SH_PFC_PIN_GROUP(ceu_data_8_15), - SH_PFC_PIN_GROUP(ceu_clk_0), - SH_PFC_PIN_GROUP(ceu_clk_1), - SH_PFC_PIN_GROUP(ceu_clk_2), - SH_PFC_PIN_GROUP(ceu_sync), - SH_PFC_PIN_GROUP(ceu_field), - SH_PFC_PIN_GROUP(flctl_data), - SH_PFC_PIN_GROUP(flctl_ce0), - SH_PFC_PIN_GROUP(flctl_ce1), - SH_PFC_PIN_GROUP(flctl_ctrl), - SH_PFC_PIN_GROUP(fsia_mclk_in), - SH_PFC_PIN_GROUP(fsia_mclk_out), - SH_PFC_PIN_GROUP(fsia_sclk_in), - SH_PFC_PIN_GROUP(fsia_sclk_out), - SH_PFC_PIN_GROUP(fsia_data_in), - SH_PFC_PIN_GROUP(fsia_data_out), - SH_PFC_PIN_GROUP(fsia_spdif_0), - SH_PFC_PIN_GROUP(fsia_spdif_1), - SH_PFC_PIN_GROUP(fsib_mclk_in), - SH_PFC_PIN_GROUP(hdmi), - SH_PFC_PIN_GROUP(intc_irq0_0), - SH_PFC_PIN_GROUP(intc_irq0_1), - SH_PFC_PIN_GROUP(intc_irq1), - SH_PFC_PIN_GROUP(intc_irq2_0), - SH_PFC_PIN_GROUP(intc_irq2_1), - SH_PFC_PIN_GROUP(intc_irq3_0), - SH_PFC_PIN_GROUP(intc_irq3_1), - SH_PFC_PIN_GROUP(intc_irq4_0), - SH_PFC_PIN_GROUP(intc_irq4_1), - SH_PFC_PIN_GROUP(intc_irq5), - SH_PFC_PIN_GROUP(intc_irq6_0), - SH_PFC_PIN_GROUP(intc_irq6_1), - SH_PFC_PIN_GROUP(intc_irq7_0), - SH_PFC_PIN_GROUP(intc_irq7_1), - SH_PFC_PIN_GROUP(intc_irq8_0), - SH_PFC_PIN_GROUP(intc_irq8_1), - SH_PFC_PIN_GROUP(intc_irq9_0), - SH_PFC_PIN_GROUP(intc_irq9_1), - SH_PFC_PIN_GROUP(intc_irq10), - SH_PFC_PIN_GROUP(intc_irq11), - SH_PFC_PIN_GROUP(intc_irq12_0), - SH_PFC_PIN_GROUP(intc_irq12_1), - SH_PFC_PIN_GROUP(intc_irq13_0), - SH_PFC_PIN_GROUP(intc_irq13_1), - SH_PFC_PIN_GROUP(intc_irq14_0), - SH_PFC_PIN_GROUP(intc_irq14_1), - SH_PFC_PIN_GROUP(intc_irq15_0), - SH_PFC_PIN_GROUP(intc_irq15_1), - SH_PFC_PIN_GROUP(intc_irq16_0), - SH_PFC_PIN_GROUP(intc_irq16_1), - SH_PFC_PIN_GROUP(intc_irq17), - SH_PFC_PIN_GROUP(intc_irq18), - SH_PFC_PIN_GROUP(intc_irq19), - SH_PFC_PIN_GROUP(intc_irq20), - SH_PFC_PIN_GROUP(intc_irq21), - SH_PFC_PIN_GROUP(intc_irq22), - SH_PFC_PIN_GROUP(intc_irq23), - SH_PFC_PIN_GROUP(intc_irq24), - SH_PFC_PIN_GROUP(intc_irq25), - SH_PFC_PIN_GROUP(intc_irq26_0), - SH_PFC_PIN_GROUP(intc_irq26_1), - SH_PFC_PIN_GROUP(intc_irq27_0), - SH_PFC_PIN_GROUP(intc_irq27_1), - SH_PFC_PIN_GROUP(intc_irq28_0), - SH_PFC_PIN_GROUP(intc_irq28_1), - SH_PFC_PIN_GROUP(intc_irq29_0), - SH_PFC_PIN_GROUP(intc_irq29_1), - SH_PFC_PIN_GROUP(intc_irq30_0), - SH_PFC_PIN_GROUP(intc_irq30_1), - SH_PFC_PIN_GROUP(intc_irq31_0), - SH_PFC_PIN_GROUP(intc_irq31_1), - SH_PFC_PIN_GROUP(keysc_in04_0), - SH_PFC_PIN_GROUP(keysc_in04_1), - SH_PFC_PIN_GROUP(keysc_in5), - SH_PFC_PIN_GROUP(keysc_in6), - SH_PFC_PIN_GROUP(keysc_in7), - SH_PFC_PIN_GROUP(keysc_out4), - SH_PFC_PIN_GROUP(keysc_out5), - SH_PFC_PIN_GROUP(keysc_out6), - SH_PFC_PIN_GROUP(keysc_out8), - SH_PFC_PIN_GROUP(lcd_data8), - SH_PFC_PIN_GROUP(lcd_data9), - SH_PFC_PIN_GROUP(lcd_data12), - SH_PFC_PIN_GROUP(lcd_data16), - SH_PFC_PIN_GROUP(lcd_data18), - SH_PFC_PIN_GROUP(lcd_data24), - SH_PFC_PIN_GROUP(lcd_display), - SH_PFC_PIN_GROUP(lcd_lclk), - SH_PFC_PIN_GROUP(lcd_sync), - SH_PFC_PIN_GROUP(lcd_sys), - SH_PFC_PIN_GROUP(mmc0_data1_0), - SH_PFC_PIN_GROUP(mmc0_data4_0), - SH_PFC_PIN_GROUP(mmc0_data8_0), - SH_PFC_PIN_GROUP(mmc0_ctrl_0), - SH_PFC_PIN_GROUP(mmc0_data1_1), - SH_PFC_PIN_GROUP(mmc0_data4_1), - SH_PFC_PIN_GROUP(mmc0_data8_1), - SH_PFC_PIN_GROUP(mmc0_ctrl_1), - SH_PFC_PIN_GROUP(scifa0_data), - SH_PFC_PIN_GROUP(scifa0_clk), - SH_PFC_PIN_GROUP(scifa0_ctrl), - SH_PFC_PIN_GROUP(scifa1_data), - SH_PFC_PIN_GROUP(scifa1_clk), - SH_PFC_PIN_GROUP(scifa1_ctrl), - SH_PFC_PIN_GROUP(scifa2_data), - SH_PFC_PIN_GROUP(scifa2_clk), - SH_PFC_PIN_GROUP(scifa2_ctrl), - SH_PFC_PIN_GROUP(scifa3_data), - SH_PFC_PIN_GROUP(scifa3_clk), - SH_PFC_PIN_GROUP(scifa3_ctrl_0), - SH_PFC_PIN_GROUP(scifa3_ctrl_1), - SH_PFC_PIN_GROUP(scifa4_data), - SH_PFC_PIN_GROUP(scifa5_data), - SH_PFC_PIN_GROUP(scifb_data), - SH_PFC_PIN_GROUP(scifb_clk), - SH_PFC_PIN_GROUP(scifb_ctrl), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(usb0_vbus), - SH_PFC_PIN_GROUP(usb0_otg_id), - SH_PFC_PIN_GROUP(usb0_otg_ctrl), - SH_PFC_PIN_GROUP(usb1_vbus), - SH_PFC_PIN_GROUP(usb1_otg_id_0), - SH_PFC_PIN_GROUP(usb1_otg_id_1), - SH_PFC_PIN_GROUP(usb1_otg_ctrl_0), - SH_PFC_PIN_GROUP(usb1_otg_ctrl_1), -}; - -static const char * const bsc_groups[] = { - "bsc_data8", - "bsc_data16", - "bsc_cs0", - "bsc_cs2", - "bsc_cs4", - "bsc_cs5a", - "bsc_cs5b", - "bsc_cs6a", - "bsc_rd_we8", - "bsc_rd_we16", - "bsc_bs", - "bsc_rdwr", -}; - -static const char * const ceu_groups[] = { - "ceu_data_0_7", - "ceu_data_8_15", - "ceu_clk_0", - "ceu_clk_1", - "ceu_clk_2", - "ceu_sync", - "ceu_field", -}; - -static const char * const flctl_groups[] = { - "flctl_data", - "flctl_ce0", - "flctl_ce1", - "flctl_ctrl", -}; - -static const char * const fsia_groups[] = { - "fsia_mclk_in", - "fsia_mclk_out", - "fsia_sclk_in", - "fsia_sclk_out", - "fsia_data_in", - "fsia_data_out", - "fsia_spdif_0", - "fsia_spdif_1", -}; - -static const char * const fsib_groups[] = { - "fsib_mclk_in", -}; - -static const char * const hdmi_groups[] = { - "hdmi", -}; - -static const char * const intc_groups[] = { - "intc_irq0_0", - "intc_irq0_1", - "intc_irq1", - "intc_irq2_0", - "intc_irq2_1", - "intc_irq3_0", - "intc_irq3_1", - "intc_irq4_0", - "intc_irq4_1", - "intc_irq5", - "intc_irq6_0", - "intc_irq6_1", - "intc_irq7_0", - "intc_irq7_1", - "intc_irq8_0", - "intc_irq8_1", - "intc_irq9_0", - "intc_irq9_1", - "intc_irq10", - "intc_irq11", - "intc_irq12_0", - "intc_irq12_1", - "intc_irq13_0", - "intc_irq13_1", - "intc_irq14_0", - "intc_irq14_1", - "intc_irq15_0", - "intc_irq15_1", - "intc_irq16_0", - "intc_irq16_1", - "intc_irq17", - "intc_irq18", - "intc_irq19", - "intc_irq20", - "intc_irq21", - "intc_irq22", - "intc_irq23", - "intc_irq24", - "intc_irq25", - "intc_irq26_0", - "intc_irq26_1", - "intc_irq27_0", - "intc_irq27_1", - "intc_irq28_0", - "intc_irq28_1", - "intc_irq29_0", - "intc_irq29_1", - "intc_irq30_0", - "intc_irq30_1", - "intc_irq31_0", - "intc_irq31_1", -}; - -static const char * const keysc_groups[] = { - "keysc_in04_0", - "keysc_in04_1", - "keysc_in5", - "keysc_in6", - "keysc_in7", - "keysc_out4", - "keysc_out5", - "keysc_out6", - "keysc_out8", -}; - -static const char * const lcd_groups[] = { - "lcd_data8", - "lcd_data9", - "lcd_data12", - "lcd_data16", - "lcd_data18", - "lcd_data24", - "lcd_display", - "lcd_lclk", - "lcd_sync", - "lcd_sys", -}; - -static const char * const mmc0_groups[] = { - "mmc0_data1_0", - "mmc0_data4_0", - "mmc0_data8_0", - "mmc0_ctrl_0", - "mmc0_data1_1", - "mmc0_data4_1", - "mmc0_data8_1", - "mmc0_ctrl_1", -}; - -static const char * const scifa0_groups[] = { - "scifa0_data", - "scifa0_clk", - "scifa0_ctrl", -}; - -static const char * const scifa1_groups[] = { - "scifa1_data", - "scifa1_clk", - "scifa1_ctrl", -}; - -static const char * const scifa2_groups[] = { - "scifa2_data", - "scifa2_clk", - "scifa2_ctrl", -}; - -static const char * const scifa3_groups[] = { - "scifa3_data", - "scifa3_clk", - "scifa3_ctrl_0", - "scifa3_ctrl_1", -}; - -static const char * const scifa4_groups[] = { - "scifa4_data", -}; - -static const char * const scifa5_groups[] = { - "scifa5_data", -}; - -static const char * const scifb_groups[] = { - "scifb_data", - "scifb_clk", - "scifb_ctrl", -}; - -static const char * const sdhi0_groups[] = { - "sdhi0_data1", - "sdhi0_data4", - "sdhi0_ctrl", - "sdhi0_cd", - "sdhi0_wp", -}; - -static const char * const sdhi1_groups[] = { - "sdhi1_data1", - "sdhi1_data4", - "sdhi1_ctrl", -}; - -static const char * const sdhi2_groups[] = { - "sdhi2_data1", - "sdhi2_data4", - "sdhi2_ctrl", -}; - -static const char * const usb0_groups[] = { - "usb0_vbus", - "usb0_otg_id", - "usb0_otg_ctrl", -}; - -static const char * const usb1_groups[] = { - "usb1_vbus", - "usb1_otg_id_0", - "usb1_otg_id_1", - "usb1_otg_ctrl_0", - "usb1_otg_ctrl_1", -}; - -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(bsc), - SH_PFC_FUNCTION(ceu), - SH_PFC_FUNCTION(flctl), - SH_PFC_FUNCTION(fsia), - SH_PFC_FUNCTION(fsib), - SH_PFC_FUNCTION(hdmi), - SH_PFC_FUNCTION(intc), - SH_PFC_FUNCTION(keysc), - SH_PFC_FUNCTION(lcd), - SH_PFC_FUNCTION(mmc0), - SH_PFC_FUNCTION(scifa0), - SH_PFC_FUNCTION(scifa1), - SH_PFC_FUNCTION(scifa2), - SH_PFC_FUNCTION(scifa3), - SH_PFC_FUNCTION(scifa4), - SH_PFC_FUNCTION(scifa5), - SH_PFC_FUNCTION(scifb), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(usb0), - SH_PFC_FUNCTION(usb1), -}; - -static const struct pinmux_cfg_reg pinmux_config_regs[] = { - PORTCR(0, 0xE6051000), /* PORT0CR */ - PORTCR(1, 0xE6051001), /* PORT1CR */ - PORTCR(2, 0xE6051002), /* PORT2CR */ - PORTCR(3, 0xE6051003), /* PORT3CR */ - PORTCR(4, 0xE6051004), /* PORT4CR */ - PORTCR(5, 0xE6051005), /* PORT5CR */ - PORTCR(6, 0xE6051006), /* PORT6CR */ - PORTCR(7, 0xE6051007), /* PORT7CR */ - PORTCR(8, 0xE6051008), /* PORT8CR */ - PORTCR(9, 0xE6051009), /* PORT9CR */ - PORTCR(10, 0xE605100A), /* PORT10CR */ - PORTCR(11, 0xE605100B), /* PORT11CR */ - PORTCR(12, 0xE605100C), /* PORT12CR */ - PORTCR(13, 0xE605100D), /* PORT13CR */ - PORTCR(14, 0xE605100E), /* PORT14CR */ - PORTCR(15, 0xE605100F), /* PORT15CR */ - PORTCR(16, 0xE6051010), /* PORT16CR */ - PORTCR(17, 0xE6051011), /* PORT17CR */ - PORTCR(18, 0xE6051012), /* PORT18CR */ - PORTCR(19, 0xE6051013), /* PORT19CR */ - PORTCR(20, 0xE6051014), /* PORT20CR */ - PORTCR(21, 0xE6051015), /* PORT21CR */ - PORTCR(22, 0xE6051016), /* PORT22CR */ - PORTCR(23, 0xE6051017), /* PORT23CR */ - PORTCR(24, 0xE6051018), /* PORT24CR */ - PORTCR(25, 0xE6051019), /* PORT25CR */ - PORTCR(26, 0xE605101A), /* PORT26CR */ - PORTCR(27, 0xE605101B), /* PORT27CR */ - PORTCR(28, 0xE605101C), /* PORT28CR */ - PORTCR(29, 0xE605101D), /* PORT29CR */ - PORTCR(30, 0xE605101E), /* PORT30CR */ - PORTCR(31, 0xE605101F), /* PORT31CR */ - PORTCR(32, 0xE6051020), /* PORT32CR */ - PORTCR(33, 0xE6051021), /* PORT33CR */ - PORTCR(34, 0xE6051022), /* PORT34CR */ - PORTCR(35, 0xE6051023), /* PORT35CR */ - PORTCR(36, 0xE6051024), /* PORT36CR */ - PORTCR(37, 0xE6051025), /* PORT37CR */ - PORTCR(38, 0xE6051026), /* PORT38CR */ - PORTCR(39, 0xE6051027), /* PORT39CR */ - PORTCR(40, 0xE6051028), /* PORT40CR */ - PORTCR(41, 0xE6051029), /* PORT41CR */ - PORTCR(42, 0xE605102A), /* PORT42CR */ - PORTCR(43, 0xE605102B), /* PORT43CR */ - PORTCR(44, 0xE605102C), /* PORT44CR */ - PORTCR(45, 0xE605102D), /* PORT45CR */ - PORTCR(46, 0xE605202E), /* PORT46CR */ - PORTCR(47, 0xE605202F), /* PORT47CR */ - PORTCR(48, 0xE6052030), /* PORT48CR */ - PORTCR(49, 0xE6052031), /* PORT49CR */ - PORTCR(50, 0xE6052032), /* PORT50CR */ - PORTCR(51, 0xE6052033), /* PORT51CR */ - PORTCR(52, 0xE6052034), /* PORT52CR */ - PORTCR(53, 0xE6052035), /* PORT53CR */ - PORTCR(54, 0xE6052036), /* PORT54CR */ - PORTCR(55, 0xE6052037), /* PORT55CR */ - PORTCR(56, 0xE6052038), /* PORT56CR */ - PORTCR(57, 0xE6052039), /* PORT57CR */ - PORTCR(58, 0xE605203A), /* PORT58CR */ - PORTCR(59, 0xE605203B), /* PORT59CR */ - PORTCR(60, 0xE605203C), /* PORT60CR */ - PORTCR(61, 0xE605203D), /* PORT61CR */ - PORTCR(62, 0xE605203E), /* PORT62CR */ - PORTCR(63, 0xE605203F), /* PORT63CR */ - PORTCR(64, 0xE6052040), /* PORT64CR */ - PORTCR(65, 0xE6052041), /* PORT65CR */ - PORTCR(66, 0xE6052042), /* PORT66CR */ - PORTCR(67, 0xE6052043), /* PORT67CR */ - PORTCR(68, 0xE6052044), /* PORT68CR */ - PORTCR(69, 0xE6052045), /* PORT69CR */ - PORTCR(70, 0xE6052046), /* PORT70CR */ - PORTCR(71, 0xE6052047), /* PORT71CR */ - PORTCR(72, 0xE6052048), /* PORT72CR */ - PORTCR(73, 0xE6052049), /* PORT73CR */ - PORTCR(74, 0xE605204A), /* PORT74CR */ - PORTCR(75, 0xE605204B), /* PORT75CR */ - PORTCR(76, 0xE605004C), /* PORT76CR */ - PORTCR(77, 0xE605004D), /* PORT77CR */ - PORTCR(78, 0xE605004E), /* PORT78CR */ - PORTCR(79, 0xE605004F), /* PORT79CR */ - PORTCR(80, 0xE6050050), /* PORT80CR */ - PORTCR(81, 0xE6050051), /* PORT81CR */ - PORTCR(82, 0xE6050052), /* PORT82CR */ - PORTCR(83, 0xE6050053), /* PORT83CR */ - PORTCR(84, 0xE6050054), /* PORT84CR */ - PORTCR(85, 0xE6050055), /* PORT85CR */ - PORTCR(86, 0xE6050056), /* PORT86CR */ - PORTCR(87, 0xE6050057), /* PORT87CR */ - PORTCR(88, 0xE6050058), /* PORT88CR */ - PORTCR(89, 0xE6050059), /* PORT89CR */ - PORTCR(90, 0xE605005A), /* PORT90CR */ - PORTCR(91, 0xE605005B), /* PORT91CR */ - PORTCR(92, 0xE605005C), /* PORT92CR */ - PORTCR(93, 0xE605005D), /* PORT93CR */ - PORTCR(94, 0xE605005E), /* PORT94CR */ - PORTCR(95, 0xE605005F), /* PORT95CR */ - PORTCR(96, 0xE6050060), /* PORT96CR */ - PORTCR(97, 0xE6050061), /* PORT97CR */ - PORTCR(98, 0xE6050062), /* PORT98CR */ - PORTCR(99, 0xE6050063), /* PORT99CR */ - PORTCR(100, 0xE6053064), /* PORT100CR */ - PORTCR(101, 0xE6053065), /* PORT101CR */ - PORTCR(102, 0xE6053066), /* PORT102CR */ - PORTCR(103, 0xE6053067), /* PORT103CR */ - PORTCR(104, 0xE6053068), /* PORT104CR */ - PORTCR(105, 0xE6053069), /* PORT105CR */ - PORTCR(106, 0xE605306A), /* PORT106CR */ - PORTCR(107, 0xE605306B), /* PORT107CR */ - PORTCR(108, 0xE605306C), /* PORT108CR */ - PORTCR(109, 0xE605306D), /* PORT109CR */ - PORTCR(110, 0xE605306E), /* PORT110CR */ - PORTCR(111, 0xE605306F), /* PORT111CR */ - PORTCR(112, 0xE6053070), /* PORT112CR */ - PORTCR(113, 0xE6053071), /* PORT113CR */ - PORTCR(114, 0xE6053072), /* PORT114CR */ - PORTCR(115, 0xE6053073), /* PORT115CR */ - PORTCR(116, 0xE6053074), /* PORT116CR */ - PORTCR(117, 0xE6053075), /* PORT117CR */ - PORTCR(118, 0xE6053076), /* PORT118CR */ - PORTCR(119, 0xE6053077), /* PORT119CR */ - PORTCR(120, 0xE6053078), /* PORT120CR */ - PORTCR(121, 0xE6050079), /* PORT121CR */ - PORTCR(122, 0xE605007A), /* PORT122CR */ - PORTCR(123, 0xE605007B), /* PORT123CR */ - PORTCR(124, 0xE605007C), /* PORT124CR */ - PORTCR(125, 0xE605007D), /* PORT125CR */ - PORTCR(126, 0xE605007E), /* PORT126CR */ - PORTCR(127, 0xE605007F), /* PORT127CR */ - PORTCR(128, 0xE6050080), /* PORT128CR */ - PORTCR(129, 0xE6050081), /* PORT129CR */ - PORTCR(130, 0xE6050082), /* PORT130CR */ - PORTCR(131, 0xE6050083), /* PORT131CR */ - PORTCR(132, 0xE6050084), /* PORT132CR */ - PORTCR(133, 0xE6050085), /* PORT133CR */ - PORTCR(134, 0xE6050086), /* PORT134CR */ - PORTCR(135, 0xE6050087), /* PORT135CR */ - PORTCR(136, 0xE6050088), /* PORT136CR */ - PORTCR(137, 0xE6050089), /* PORT137CR */ - PORTCR(138, 0xE605008A), /* PORT138CR */ - PORTCR(139, 0xE605008B), /* PORT139CR */ - PORTCR(140, 0xE605008C), /* PORT140CR */ - PORTCR(141, 0xE605008D), /* PORT141CR */ - PORTCR(142, 0xE605008E), /* PORT142CR */ - PORTCR(143, 0xE605008F), /* PORT143CR */ - PORTCR(144, 0xE6050090), /* PORT144CR */ - PORTCR(145, 0xE6050091), /* PORT145CR */ - PORTCR(146, 0xE6050092), /* PORT146CR */ - PORTCR(147, 0xE6050093), /* PORT147CR */ - PORTCR(148, 0xE6050094), /* PORT148CR */ - PORTCR(149, 0xE6050095), /* PORT149CR */ - PORTCR(150, 0xE6050096), /* PORT150CR */ - PORTCR(151, 0xE6050097), /* PORT151CR */ - PORTCR(152, 0xE6053098), /* PORT152CR */ - PORTCR(153, 0xE6053099), /* PORT153CR */ - PORTCR(154, 0xE605309A), /* PORT154CR */ - PORTCR(155, 0xE605309B), /* PORT155CR */ - PORTCR(156, 0xE605009C), /* PORT156CR */ - PORTCR(157, 0xE605009D), /* PORT157CR */ - PORTCR(158, 0xE605009E), /* PORT158CR */ - PORTCR(159, 0xE605009F), /* PORT159CR */ - PORTCR(160, 0xE60500A0), /* PORT160CR */ - PORTCR(161, 0xE60500A1), /* PORT161CR */ - PORTCR(162, 0xE60500A2), /* PORT162CR */ - PORTCR(163, 0xE60500A3), /* PORT163CR */ - PORTCR(164, 0xE60500A4), /* PORT164CR */ - PORTCR(165, 0xE60500A5), /* PORT165CR */ - PORTCR(166, 0xE60500A6), /* PORT166CR */ - PORTCR(167, 0xE60520A7), /* PORT167CR */ - PORTCR(168, 0xE60520A8), /* PORT168CR */ - PORTCR(169, 0xE60520A9), /* PORT169CR */ - PORTCR(170, 0xE60520AA), /* PORT170CR */ - PORTCR(171, 0xE60520AB), /* PORT171CR */ - PORTCR(172, 0xE60520AC), /* PORT172CR */ - PORTCR(173, 0xE60520AD), /* PORT173CR */ - PORTCR(174, 0xE60520AE), /* PORT174CR */ - PORTCR(175, 0xE60520AF), /* PORT175CR */ - PORTCR(176, 0xE60520B0), /* PORT176CR */ - PORTCR(177, 0xE60520B1), /* PORT177CR */ - PORTCR(178, 0xE60520B2), /* PORT178CR */ - PORTCR(179, 0xE60520B3), /* PORT179CR */ - PORTCR(180, 0xE60520B4), /* PORT180CR */ - PORTCR(181, 0xE60520B5), /* PORT181CR */ - PORTCR(182, 0xE60520B6), /* PORT182CR */ - PORTCR(183, 0xE60520B7), /* PORT183CR */ - PORTCR(184, 0xE60520B8), /* PORT184CR */ - PORTCR(185, 0xE60520B9), /* PORT185CR */ - PORTCR(186, 0xE60520BA), /* PORT186CR */ - PORTCR(187, 0xE60520BB), /* PORT187CR */ - PORTCR(188, 0xE60520BC), /* PORT188CR */ - PORTCR(189, 0xE60520BD), /* PORT189CR */ - PORTCR(190, 0xE60520BE), /* PORT190CR */ - - { PINMUX_CFG_REG("MSEL1CR", 0xE605800C, 32, 1) { - MSEL1CR_31_0, MSEL1CR_31_1, - MSEL1CR_30_0, MSEL1CR_30_1, - MSEL1CR_29_0, MSEL1CR_29_1, - MSEL1CR_28_0, MSEL1CR_28_1, - MSEL1CR_27_0, MSEL1CR_27_1, - MSEL1CR_26_0, MSEL1CR_26_1, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - MSEL1CR_16_0, MSEL1CR_16_1, - MSEL1CR_15_0, MSEL1CR_15_1, - MSEL1CR_14_0, MSEL1CR_14_1, - MSEL1CR_13_0, MSEL1CR_13_1, - MSEL1CR_12_0, MSEL1CR_12_1, - 0, 0, 0, 0, - MSEL1CR_9_0, MSEL1CR_9_1, - MSEL1CR_8_0, MSEL1CR_8_1, - MSEL1CR_7_0, MSEL1CR_7_1, - MSEL1CR_6_0, MSEL1CR_6_1, - 0, 0, - MSEL1CR_4_0, MSEL1CR_4_1, - MSEL1CR_3_0, MSEL1CR_3_1, - MSEL1CR_2_0, MSEL1CR_2_1, - 0, 0, - MSEL1CR_0_0, MSEL1CR_0_1, - } - }, - { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) { - 0, 0, 0, 0, - 0, 0, 0, 0, - MSEL3CR_27_0, MSEL3CR_27_1, - MSEL3CR_26_0, MSEL3CR_26_1, - 0, 0, 0, 0, - 0, 0, 0, 0, - MSEL3CR_21_0, MSEL3CR_21_1, - MSEL3CR_20_0, MSEL3CR_20_1, - 0, 0, 0, 0, - 0, 0, 0, 0, - MSEL3CR_15_0, MSEL3CR_15_1, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, - MSEL3CR_9_0, MSEL3CR_9_1, - 0, 0, 0, 0, - MSEL3CR_6_0, MSEL3CR_6_1, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - MSEL4CR_19_0, MSEL4CR_19_1, - MSEL4CR_18_0, MSEL4CR_18_1, - MSEL4CR_17_0, MSEL4CR_17_1, - MSEL4CR_16_0, MSEL4CR_16_1, - MSEL4CR_15_0, MSEL4CR_15_1, - MSEL4CR_14_0, MSEL4CR_14_1, - 0, 0, 0, 0, - 0, 0, - MSEL4CR_10_0, MSEL4CR_10_1, - 0, 0, 0, 0, - 0, 0, - MSEL4CR_6_0, MSEL4CR_6_1, - 0, 0, - MSEL4CR_4_0, MSEL4CR_4_1, - 0, 0, 0, 0, - MSEL4CR_1_0, MSEL4CR_1_1, - 0, 0, - } - }, - { }, -}; - -static const struct pinmux_data_reg pinmux_data_regs[] = { - { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) { - PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, - PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, - PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, - PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, - PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_DATA_REG("PORTL127_096DR", 0xE605400C, 32) { - PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA, - PORT123_DATA, PORT122_DATA, PORT121_DATA, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA, - } - }, - { PINMUX_DATA_REG("PORTL159_128DR", 0xE6054010, 32) { - PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, - 0, 0, 0, 0, - PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, - PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, - PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, - PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, - PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, - PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA, - } - }, - { PINMUX_DATA_REG("PORTL191_160DR", 0xE6054014, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, PORT166_DATA, PORT165_DATA, PORT164_DATA, - PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA, - } - }, - { PINMUX_DATA_REG("PORTD031_000DR", 0xE6055000, 32) { - PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, - PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, - PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, - PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, - PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, - PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, - PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, - PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA, - } - }, - { PINMUX_DATA_REG("PORTD063_032DR", 0xE6055004, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, PORT45_DATA, PORT44_DATA, - PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, - PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, - PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA, - } - }, - { PINMUX_DATA_REG("PORTR063_032DR", 0xE6056004, 32) { - PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, - PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, - PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, - PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, - PORT47_DATA, PORT46_DATA, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_DATA_REG("PORTR095_064DR", 0xE6056008, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, - PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, - PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA, - } - }, - { PINMUX_DATA_REG("PORTR191_160DR", 0xE6056014, 32) { - 0, PORT190_DATA, PORT189_DATA, PORT188_DATA, - PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA, - PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA, - PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA, - PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA, - PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, - PORT167_DATA, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_DATA_REG("PORTU127_096DR", 0xE605700C, 32) { - 0, 0, 0, 0, - 0, 0, 0, PORT120_DATA, - PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, - PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, - PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, - PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, - PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, - 0, 0, 0, 0, - } - }, - { PINMUX_DATA_REG("PORTU159_128DR", 0xE6057010, 32) { - 0, 0, 0, 0, - PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { }, -}; - -#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5)) -#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5)) -static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(EXT_IRQ16L(0), 6, 162), - PINMUX_IRQ(EXT_IRQ16L(1), 12), - PINMUX_IRQ(EXT_IRQ16L(2), 4, 5), - PINMUX_IRQ(EXT_IRQ16L(3), 8, 16), - PINMUX_IRQ(EXT_IRQ16L(4), 17, 163), - PINMUX_IRQ(EXT_IRQ16L(5), 18), - PINMUX_IRQ(EXT_IRQ16L(6), 39, 164), - PINMUX_IRQ(EXT_IRQ16L(7), 40, 167), - PINMUX_IRQ(EXT_IRQ16L(8), 41, 168), - PINMUX_IRQ(EXT_IRQ16L(9), 42, 169), - PINMUX_IRQ(EXT_IRQ16L(10), 65), - PINMUX_IRQ(EXT_IRQ16L(11), 67), - PINMUX_IRQ(EXT_IRQ16L(12), 80, 137), - PINMUX_IRQ(EXT_IRQ16L(13), 81, 145), - PINMUX_IRQ(EXT_IRQ16L(14), 82, 146), - PINMUX_IRQ(EXT_IRQ16L(15), 83, 147), - PINMUX_IRQ(EXT_IRQ16H(16), 84, 170), - PINMUX_IRQ(EXT_IRQ16H(17), 85), - PINMUX_IRQ(EXT_IRQ16H(18), 86), - PINMUX_IRQ(EXT_IRQ16H(19), 87), - PINMUX_IRQ(EXT_IRQ16H(20), 92), - PINMUX_IRQ(EXT_IRQ16H(21), 93), - PINMUX_IRQ(EXT_IRQ16H(22), 94), - PINMUX_IRQ(EXT_IRQ16H(23), 95), - PINMUX_IRQ(EXT_IRQ16H(24), 112), - PINMUX_IRQ(EXT_IRQ16H(25), 119), - PINMUX_IRQ(EXT_IRQ16H(26), 121, 172), - PINMUX_IRQ(EXT_IRQ16H(27), 122, 180), - PINMUX_IRQ(EXT_IRQ16H(28), 123, 181), - PINMUX_IRQ(EXT_IRQ16H(29), 129, 182), - PINMUX_IRQ(EXT_IRQ16H(30), 130, 183), - PINMUX_IRQ(EXT_IRQ16H(31), 138, 184), -}; - -#define PORTnCR_PULMD_OFF (0 << 6) -#define PORTnCR_PULMD_DOWN (2 << 6) -#define PORTnCR_PULMD_UP (3 << 6) -#define PORTnCR_PULMD_MASK (3 << 6) - -struct sh7372_portcr_group { - unsigned int end_pin; - unsigned int offset; -}; - -static const struct sh7372_portcr_group sh7372_portcr_offsets[] = { - { 45, 0x1000 }, { 75, 0x2000 }, { 99, 0x0000 }, { 120, 0x3000 }, - { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 }, -}; - -static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) { - const struct sh7372_portcr_group *group = - &sh7372_portcr_offsets[i]; - - if (pin <= group->end_pin) - return pfc->windows->virt + group->offset + pin; - } - - return NULL; -} - -static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) -{ - void __iomem *addr = sh7372_pinmux_portcr(pfc, pin); - u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; - - switch (value) { - case PORTnCR_PULMD_UP: - return PIN_CONFIG_BIAS_PULL_UP; - case PORTnCR_PULMD_DOWN: - return PIN_CONFIG_BIAS_PULL_DOWN; - case PORTnCR_PULMD_OFF: - default: - return PIN_CONFIG_BIAS_DISABLE; - } -} - -static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - void __iomem *addr = sh7372_pinmux_portcr(pfc, pin); - u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; - - switch (bias) { - case PIN_CONFIG_BIAS_PULL_UP: - value |= PORTnCR_PULMD_UP; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - value |= PORTnCR_PULMD_DOWN; - break; - } - - iowrite8(value, addr); -} - -static const struct sh_pfc_soc_operations sh7372_pfc_ops = { - .get_bias = sh7372_pinmux_get_bias, - .set_bias = sh7372_pinmux_set_bias, -}; - -const struct sh_pfc_soc_info sh7372_pinmux_info = { - .name = "sh7372_pfc", - .ops = &sh7372_pfc_ops, - - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), - - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), - - .gpio_irq = pinmux_irqs, - .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), -}; diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 910deaefa0ac..072e7c62cab7 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -122,7 +122,7 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, return ret; } - ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); + ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); if (ret < 0) return ret; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 5b7283182c1e..c83728626906 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -167,6 +167,8 @@ struct sh_pfc_soc_info { PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) #define PINMUX_IPSR_NOGM(ispr, fn, ms) \ PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms) +#define PINMUX_IPSR_NOFN(ipsr, fn, ms) \ + PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms) #define PINMUX_IPSR_MSEL(ipsr, fn, ms) \ PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms) #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \ diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 4871647c7f85..2a1f07249b2f 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -38,7 +38,6 @@ struct sirfsoc_gpio_bank { struct sirfsoc_gpio_chip { struct of_mm_gpio_chip chip; - bool is_marco; /* for marco, some registers are different with prima2 */ struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; }; @@ -149,23 +148,14 @@ static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, for (i = 0; i < mux->muxmask_counts; i++) { u32 muxval; - if (!spmx->is_marco) { - muxval = readl(spmx->gpio_virtbase + - SIRFSOC_GPIO_PAD_EN(mask[i].group)); - if (enable) - muxval = muxval & ~mask[i].mask; - else - muxval = muxval | mask[i].mask; - writel(muxval, spmx->gpio_virtbase + - SIRFSOC_GPIO_PAD_EN(mask[i].group)); - } else { - if (enable) - writel(mask[i].mask, spmx->gpio_virtbase + - SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group)); - else - writel(mask[i].mask, spmx->gpio_virtbase + - SIRFSOC_GPIO_PAD_EN(mask[i].group)); - } + muxval = readl(spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(mask[i].group)); + if (enable) + muxval = muxval & ~mask[i].mask; + else + muxval = muxval | mask[i].mask; + writel(muxval, spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(mask[i].group)); } if (mux->funcmask && enable) { @@ -223,16 +213,11 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, spmx = pinctrl_dev_get_drvdata(pmxdev); - if (!spmx->is_marco) { - muxval = readl(spmx->gpio_virtbase + - SIRFSOC_GPIO_PAD_EN(group)); - muxval = muxval | (1 << (offset - range->pin_base)); - writel(muxval, spmx->gpio_virtbase + - SIRFSOC_GPIO_PAD_EN(group)); - } else { - writel(1 << (offset - range->pin_base), spmx->gpio_virtbase + - SIRFSOC_GPIO_PAD_EN(group)); - } + muxval = readl(spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(group)); + muxval = muxval | (1 << (offset - range->pin_base)); + writel(muxval, spmx->gpio_virtbase + + SIRFSOC_GPIO_PAD_EN(group)); return 0; } @@ -256,7 +241,6 @@ static void __iomem *sirfsoc_rsc_of_iomap(void) { const struct of_device_id rsc_ids[] = { { .compatible = "sirf,prima2-rsc" }, - { .compatible = "sirf,marco-rsc" }, {} }; struct device_node *np; @@ -284,7 +268,6 @@ static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, static const struct of_device_id pinmux_ids[] = { { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, }, { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, }, - { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, }, {} }; @@ -317,9 +300,6 @@ static int sirfsoc_pinmux_probe(struct platform_device *pdev) goto out_no_rsc_remap; } - if (of_device_is_compatible(np, "sirf,marco-pinctrl")) - spmx->is_marco = 1; - pdata = of_match_node(pinmux_ids, np)->data; sirfsoc_pin_groups = pdata->grps; sirfsoc_pingrp_cnt = pdata->grps_cnt; @@ -803,7 +783,6 @@ static int sirfsoc_gpio_probe(struct device_node *np) struct sirfsoc_gpio_bank *bank; void __iomem *regs; struct platform_device *pdev; - bool is_marco = false; u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; @@ -819,9 +798,6 @@ static int sirfsoc_gpio_probe(struct device_node *np) if (!regs) return -ENOMEM; - if (of_device_is_compatible(np, "sirf,marco-pinctrl")) - is_marco = 1; - sgpio->chip.gc.request = sirfsoc_gpio_request; sgpio->chip.gc.free = sirfsoc_gpio_free; sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input; @@ -836,7 +812,6 @@ static int sirfsoc_gpio_probe(struct device_node *np) sgpio->chip.gc.of_gpio_n_cells = 2; sgpio->chip.gc.dev = &pdev->dev; sgpio->chip.regs = regs; - sgpio->is_marco = is_marco; err = gpiochip_add(&sgpio->chip.gc); if (err) { diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.h b/drivers/pinctrl/sirf/pinctrl-sirf.h index d7f16b499ad9..9550335fe57a 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.h +++ b/drivers/pinctrl/sirf/pinctrl-sirf.h @@ -49,7 +49,6 @@ struct sirfsoc_pmx { u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS]; u32 dspen_regs; u32 rsc_regs[3]; - bool is_marco; }; /* SIRFSOC_GPIO_PAD_EN set */ diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 230a952608cb..2eb893e0ea1e 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -21,6 +21,10 @@ config PINCTRL_SUN6I_A31 def_bool MACH_SUN6I select PINCTRL_SUNXI_COMMON +config PINCTRL_SUN6I_A31S + def_bool MACH_SUN6I + select PINCTRL_SUNXI_COMMON + config PINCTRL_SUN6I_A31_R def_bool MACH_SUN6I depends on RESET_CONTROLLER diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index c7d92e4673b5..b796d579dce6 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o +obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c index f42858eaca28..18038f0d6b52 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c @@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */ + SUNXI_FUNCTION(0x4, "clk_out_a"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */ + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */ + SUNXI_FUNCTION(0x4, "dmic"), /* DIN */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */ SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */ + SUNXI_FUNCTION(0x4, "clk_out_b"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "gmac"), /* MDC */ SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "clk_out_c"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27), SUNXI_FUNCTION(0x0, "gpio_in"), diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c new file mode 100644 index 000000000000..9b5a91f610c7 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c @@ -0,0 +1,815 @@ +/* + * Allwinner A31s SoCs pinctrl driver. + * + * Copyright (C) 2014 Hans de Goede <hdegoede@redhat.com> + * + * Based on pinctrl-sun6i-a31.c, which is: + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun6i_a31s_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */ + SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */ + SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */ + SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */ + SUNXI_FUNCTION(0x4, "uart1"), /* RING */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */ + SUNXI_FUNCTION(0x4, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */ + SUNXI_FUNCTION(0x4, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */ + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */ + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */ + SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */ + SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */ + SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */ + SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */ + SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */ + SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */ + SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */ + SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */ + SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */ + SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */ + SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */ + SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */ + SUNXI_FUNCTION(0x4, "clk_out_a"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */ + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */ + SUNXI_FUNCTION(0x4, "dmic"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */ + SUNXI_FUNCTION(0x4, "clk_out_b"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */ + SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */ + SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */ + SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */ + SUNXI_FUNCTION(0x4, "spi3"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* COL */ + SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* CRS */ + SUNXI_FUNCTION(0x4, "spi3"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */ + SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* MDC */ + SUNXI_FUNCTION(0x4, "clk_out_c"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s0"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* RE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */ + SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */ + SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */ + SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */ + /* Hole in pin numbering ! */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2"), /* RST */ + SUNXI_FUNCTION(0x4, "mmc3")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x3, "ts"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION(0x3, "ts"), /* ERR */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "ts"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "ts"), /* DVLD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION(0x3, "uart5"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION(0x3, "uart5"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x3, "uart5"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart5"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x3, "ts"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x3, "ts"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x3, "ts"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x3, "ts"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D8 */ + SUNXI_FUNCTION(0x3, "ts"), /* D4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D9 */ + SUNXI_FUNCTION(0x3, "ts"), /* D5 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D10 */ + SUNXI_FUNCTION(0x3, "ts"), /* D6 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D11 */ + SUNXI_FUNCTION(0x3, "ts"), /* D7 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ + SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart4"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart4"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */ + /* Hole, note H starts at pin 9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ + SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ + SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ + SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ + SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm0")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), +}; + +static const struct sunxi_pinctrl_desc sun6i_a31s_pinctrl_data = { + .pins = sun6i_a31s_pins, + .npins = ARRAY_SIZE(sun6i_a31s_pins), + .irq_banks = 4, +}; + +static int sun6i_a31s_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun6i_a31s_pinctrl_data); +} + +static struct of_device_id sun6i_a31s_pinctrl_match[] = { + { .compatible = "allwinner,sun6i-a31s-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun6i_a31s_pinctrl_match); + +static struct platform_driver sun6i_a31s_pinctrl_driver = { + .probe = sun6i_a31s_pinctrl_probe, + .driver = { + .name = "sun6i-a31s-pinctrl", + .owner = THIS_MODULE, + .of_match_table = sun6i_a31s_pinctrl_match, + }, +}; +module_platform_driver(sun6i_a31s_pinctrl_driver); + +MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); +MODULE_DESCRIPTION("Allwinner A31s pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/include/dt-bindings/gpio/meson8-gpio.h b/include/dt-bindings/gpio/meson8-gpio.h new file mode 100644 index 000000000000..fdaeb5cbf5e1 --- /dev/null +++ b/include/dt-bindings/gpio/meson8-gpio.h @@ -0,0 +1,157 @@ +/* + * GPIO definitions for Amlogic Meson8 SoCs + * + * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _DT_BINDINGS_MESON8_GPIO_H +#define _DT_BINDINGS_MESON8_GPIO_H + +/* First GPIO chip */ +#define GPIOX_0 0 +#define GPIOX_1 1 +#define GPIOX_2 2 +#define GPIOX_3 3 +#define GPIOX_4 4 +#define GPIOX_5 5 +#define GPIOX_6 6 +#define GPIOX_7 7 +#define GPIOX_8 8 +#define GPIOX_9 9 +#define GPIOX_10 10 +#define GPIOX_11 11 +#define GPIOX_12 12 +#define GPIOX_13 13 +#define GPIOX_14 14 +#define GPIOX_15 15 +#define GPIOX_16 16 +#define GPIOX_17 17 +#define GPIOX_18 18 +#define GPIOX_19 19 +#define GPIOX_20 20 +#define GPIOX_21 21 +#define GPIOY_0 22 +#define GPIOY_1 23 +#define GPIOY_2 24 +#define GPIOY_3 25 +#define GPIOY_4 26 +#define GPIOY_5 27 +#define GPIOY_6 28 +#define GPIOY_7 29 +#define GPIOY_8 30 +#define GPIOY_9 31 +#define GPIOY_10 32 +#define GPIOY_11 33 +#define GPIOY_12 34 +#define GPIOY_13 35 +#define GPIOY_14 36 +#define GPIOY_15 37 +#define GPIOY_16 38 +#define GPIODV_0 39 +#define GPIODV_1 40 +#define GPIODV_2 41 +#define GPIODV_3 42 +#define GPIODV_4 43 +#define GPIODV_5 44 +#define GPIODV_6 45 +#define GPIODV_7 46 +#define GPIODV_8 47 +#define GPIODV_9 48 +#define GPIODV_10 49 +#define GPIODV_11 50 +#define GPIODV_12 51 +#define GPIODV_13 52 +#define GPIODV_14 53 +#define GPIODV_15 54 +#define GPIODV_16 55 +#define GPIODV_17 56 +#define GPIODV_18 57 +#define GPIODV_19 58 +#define GPIODV_20 59 +#define GPIODV_21 60 +#define GPIODV_22 61 +#define GPIODV_23 62 +#define GPIODV_24 63 +#define GPIODV_25 64 +#define GPIODV_26 65 +#define GPIODV_27 66 +#define GPIODV_28 67 +#define GPIODV_29 68 +#define GPIOH_0 69 +#define GPIOH_1 70 +#define GPIOH_2 71 +#define GPIOH_3 72 +#define GPIOH_4 73 +#define GPIOH_5 74 +#define GPIOH_6 75 +#define GPIOH_7 76 +#define GPIOH_8 77 +#define GPIOH_9 78 +#define GPIOZ_0 79 +#define GPIOZ_1 80 +#define GPIOZ_2 81 +#define GPIOZ_3 82 +#define GPIOZ_4 83 +#define GPIOZ_5 84 +#define GPIOZ_6 85 +#define GPIOZ_7 86 +#define GPIOZ_8 87 +#define GPIOZ_9 88 +#define GPIOZ_10 89 +#define GPIOZ_11 90 +#define GPIOZ_12 91 +#define GPIOZ_13 92 +#define GPIOZ_14 93 +#define CARD_0 94 +#define CARD_1 95 +#define CARD_2 96 +#define CARD_3 97 +#define CARD_4 98 +#define CARD_5 99 +#define CARD_6 100 +#define BOOT_0 101 +#define BOOT_1 102 +#define BOOT_2 103 +#define BOOT_3 104 +#define BOOT_4 105 +#define BOOT_5 106 +#define BOOT_6 107 +#define BOOT_7 108 +#define BOOT_8 109 +#define BOOT_9 110 +#define BOOT_10 111 +#define BOOT_11 112 +#define BOOT_12 113 +#define BOOT_13 114 +#define BOOT_14 115 +#define BOOT_15 116 +#define BOOT_16 117 +#define BOOT_17 118 +#define BOOT_18 119 + +/* Second GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOAO_12 12 +#define GPIOAO_13 13 +#define GPIO_BSD_EN 14 +#define GPIO_TEST_N 15 + +#endif /* _DT_BINDINGS_MESON8_GPIO_H */ diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h index 18eccefea06e..72c0415d6c21 100644 --- a/include/linux/pinctrl/consumer.h +++ b/include/linux/pinctrl/consumer.h @@ -82,7 +82,7 @@ static inline int pinctrl_gpio_direction_output(unsigned gpio) static inline struct pinctrl * __must_check pinctrl_get(struct device *dev) { - return NULL; + return ERR_PTR(-ENOSYS); } static inline void pinctrl_put(struct pinctrl *p) @@ -93,7 +93,7 @@ static inline struct pinctrl_state * __must_check pinctrl_lookup_state( struct pinctrl *p, const char *name) { - return NULL; + return ERR_PTR(-ENOSYS); } static inline int pinctrl_select_state(struct pinctrl *p, @@ -104,7 +104,7 @@ static inline int pinctrl_select_state(struct pinctrl *p, static inline struct pinctrl * __must_check devm_pinctrl_get(struct device *dev) { - return NULL; + return ERR_PTR(-ENOSYS); } static inline void devm_pinctrl_put(struct pinctrl *p) diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index d578a60eff23..fe65962b264f 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -115,6 +115,18 @@ enum pin_config_param { PIN_CONFIG_END = 0x7FFF, }; +#ifdef CONFIG_DEBUG_FS +#define PCONFDUMP(a, b, c, d) { .param = a, .display = b, .format = c, \ + .has_arg = d } + +struct pin_config_item { + const enum pin_config_param param; + const char * const display; + const char * const format; + bool has_arg; +}; +#endif /* CONFIG_DEBUG_FS */ + /* * Helpful configuration macro to be used in tables etc. */ @@ -150,6 +162,12 @@ static inline unsigned long pinconf_to_config_packed(enum pin_config_param param struct pinctrl_dev; struct pinctrl_map; +struct pinconf_generic_params { + const char * const property; + enum pin_config_param param; + u32 default_value; +}; + int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned *reserved_maps, unsigned *num_maps, @@ -174,6 +192,17 @@ static inline int pinconf_generic_dt_node_to_map_pin( PIN_MAP_TYPE_CONFIGS_PIN); } +static inline int pinconf_generic_dt_node_to_map_all( + struct pinctrl_dev *pctldev, struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + /* + * passing the type as PIN_MAP_TYPE_INVALID causes the underlying parser + * to infer the map type from the DT properties used. + */ + return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps, + PIN_MAP_TYPE_INVALID); +} #endif #endif /* CONFIG_GENERIC_PINCONF */ diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index cc8e1aff0e28..66e4697516de 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -24,6 +24,7 @@ struct pinctrl_dev; struct pinctrl_map; struct pinmux_ops; struct pinconf_ops; +struct pin_config_item; struct gpio_chip; struct device_node; @@ -117,6 +118,12 @@ struct pinctrl_ops { * @confops: pin config operations vtable, if you support pin configuration in * your driver * @owner: module providing the pin controller, used for refcounting + * @num_custom_params: Number of driver-specific custom parameters to be parsed + * from the hardware description + * @custom_params: List of driver_specific custom parameters to be parsed from + * the hardware description + * @custom_conf_items: Information how to print @params in debugfs, must be + * the same size as the @custom_params, i.e. @num_custom_params */ struct pinctrl_desc { const char *name; @@ -126,6 +133,11 @@ struct pinctrl_desc { const struct pinmux_ops *pmxops; const struct pinconf_ops *confops; struct module *owner; +#ifdef CONFIG_GENERIC_PINCONF + unsigned int num_custom_params; + const struct pinconf_generic_params *custom_params; + const struct pin_config_item *custom_conf_items; +#endif }; /* External interface to pin controller */ |