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authorCatalin Marinas <catalin.marinas@arm.com>2009-02-11 13:13:56 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-12 11:59:44 +0100
commit7279dc3e914635ab4b288ec39383272a06c466f3 (patch)
treefd5801c660dc1d3b262cde513ba3baaf2f89e13b
parent[ARM] 5387/1: Add ptrace VFP support on ARM (diff)
downloadlinux-7279dc3e914635ab4b288ec39383272a06c466f3.tar.xz
linux-7279dc3e914635ab4b288ec39383272a06c466f3.zip
[ARM] 5388/1: Add hwcap bits for VFPv3 and VFPv3D16
The VFPv3D16 is a VFPv3 CPU configuration where only 16 double registers are present, as the VFPv2 configuration. This patch adds the corresponding hwcap bits so that applications or debuggers have more information about the supported features. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/include/asm/hwcap.h2
-rw-r--r--arch/arm/kernel/setup.c2
-rw-r--r--arch/arm/vfp/vfpmodule.c12
3 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index bda489f9f017..f7bd52b1c365 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -17,6 +17,8 @@
#define HWCAP_CRUNCH 1024
#define HWCAP_THUMBEE 2048
#define HWCAP_NEON 4096
+#define HWCAP_VFPv3 8192
+#define HWCAP_VFPv3D16 16384
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
/*
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 7049815d66d5..645ec7436681 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -779,6 +779,8 @@ static const char *hwcap_str[] = {
"crunch",
"thumbee",
"neon",
+ "vfpv3",
+ "vfpv3d16",
NULL
};
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 7e1239041b39..75457b30d813 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -476,6 +476,18 @@ static int __init vfp_init(void)
* in place; report VFP support to userspace.
*/
elf_hwcap |= HWCAP_VFP;
+#ifdef CONFIG_VFPv3
+ if (VFP_arch >= 3) {
+ elf_hwcap |= HWCAP_VFPv3;
+
+ /*
+ * Check for VFPv3 D16. CPUs in this configuration
+ * only have 16 x 64bit registers.
+ */
+ if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK)) == 1)
+ elf_hwcap |= HWCAP_VFPv3D16;
+ }
+#endif
#ifdef CONFIG_NEON
/*
* Check for the presence of the Advanced SIMD