diff options
| author | Yunzhi Li <lyz@rock-chips.com> | 2014-12-12 16:12:21 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2015-02-23 10:12:30 +0100 |
| commit | f6db7029bb266fafe7679792514c1f26556fd61e (patch) | |
| tree | b37daef38c65a5ffb4a9863872afb37d54d7790d | |
| parent | Linux 4.0-rc1 (diff) | |
| download | linux-f6db7029bb266fafe7679792514c1f26556fd61e.tar.xz linux-f6db7029bb266fafe7679792514c1f26556fd61e.zip | |
ARM: dts: rockchip: add rk3288 usb PHY
This patch adds a device_node for RK3288 SoC usb phy. It also
defines the phy to be used by three usb controllers: usb_host0/1
and usb_otg.
Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Tested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm/boot/dts/rk3288.dtsi | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index d771f687a13b..2c29a3e8bd43 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -419,6 +419,8 @@ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_USBHOST0>; clock-names = "usbhost"; + phys = <&usbphy1>; + phy-names = "usb"; status = "disabled"; }; @@ -431,6 +433,8 @@ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_USBHOST1>; clock-names = "otg"; + phys = <&usbphy2>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -441,6 +445,8 @@ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_OTG0>; clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -697,6 +703,35 @@ interrupts = <GIC_PPI 9 0xf04>; }; + usbphy: phy { + compatible = "rockchip,rk3288-usb-phy"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy0 { + #phy-cells = <0>; + reg = <0x320>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + }; + + usbphy1: usb-phy1 { + #phy-cells = <0>; + reg = <0x334>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + }; + + usbphy2: usb-phy2 { + #phy-cells = <0>; + reg = <0x348>; + clocks = <&cru SCLK_OTGPHY2>; + clock-names = "phyclk"; + }; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3288-pinctrl"; rockchip,grf = <&grf>; |